| Topics |
Author |
Replies |
Views |
Last post |
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Verilog add-on to Vi/Vim |
Kevin C Won |
1 |
370 |
Fri, 07 Feb 2003 03:00:00 GMT
Raman Naraya
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help: Swedish Engineer to the Valley |
engine.. |
9 |
234 |
Fri, 07 Feb 2003 03:00:00 GMT
Stuart Clu
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CONSUMER ALERT - Beware of Eucalypt Software - Makers of Autopost & Rocketfuel!!! |
Warning-Warn.. |
0 |
375 |
Thu, 06 Feb 2003 03:00:00 GMT
Warning-Warn..
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fifo design |
Raja Gosul |
1 |
375 |
Thu, 06 Feb 2003 03:00:00 GMT
Srinivasan Venkataramana
|
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Gate Counts reported by Leonardo |
Tony Ha |
1 |
381 |
Tue, 04 Feb 2003 11:46:48 GMT
Muzaffer Ka
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A few simple (?) questions... |
Paul Johnso |
1 |
384 |
Tue, 04 Feb 2003 03:00:00 GMT
Paul Campbel
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Emacs verilog mode ands Silos? |
Paul Johnso |
0 |
386 |
Tue, 04 Feb 2003 03:00:00 GMT
Paul Johnso
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c model convert to verilog/VHDl model |
hche.. |
4 |
324 |
Tue, 04 Feb 2003 03:00:00 GMT
Tennisiske
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I'm looking for VLC HDL code |
Jame |
0 |
395 |
Mon, 03 Feb 2003 10:06:09 GMT
Jame
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which tool can verilog in netlist on PC |
news.hinet.ne |
0 |
393 |
Mon, 03 Feb 2003 03:00:00 GMT
news.hinet.ne
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[Fwd: Toggle event in verilog thru PLI's acc routines.] |
Pierre-Olivier Lapris |
1 |
386 |
Mon, 03 Feb 2003 03:00:00 GMT
Rabindra Guh
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How to find a ASIC job in Canada? |
zhan.. |
0 |
397 |
Mon, 03 Feb 2003 03:00:00 GMT
zhan..
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Question: how to do a fully-associative cache search |
Chun-Tao L |
0 |
394 |
Mon, 03 Feb 2003 03:00:00 GMT
Chun-Tao L
|
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PLI scope |
Pierre-Olivier Lapris |
3 |
395 |
Mon, 03 Feb 2003 03:00:00 GMT
Pierre-Olivier Lapris
|
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How Does Modelsim Traet Verilog Designs?? |
Srinivasan Venkataramana |
4 |
384 |
Sun, 02 Feb 2003 03:00:00 GMT
Srinivasan Venkataramana
|
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Problem using simwave's vcd filter |
f.. |
1 |
401 |
Sun, 02 Feb 2003 03:00:00 GMT
Srinivasan Venkataramana
|
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Document about ext vcd format wanted |
Cute Pand |
0 |
404 |
Sun, 02 Feb 2003 03:00:00 GMT
Cute Pand
|
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VHDL ieee math_real library equivalent available in Verilog |
David Bana |
1 |
408 |
Sat, 01 Feb 2003 11:01:18 GMT
Swapnajit Mittr
|
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ASIC Commodity Engineer position available |
j.. |
0 |
407 |
Sat, 01 Feb 2003 03:00:00 GMT
j..
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self-triggering always blocks ? |
Kiran |
3 |
414 |
Fri, 31 Jan 2003 03:00:00 GMT
Paul Campbel
|
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Making sense of [un]signed arithmetic and bit widths |
Chris Clar |
2 |
350 |
Fri, 31 Jan 2003 03:00:00 GMT
Chris F Clar
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asynhrous data transfer between 2 modules.. |
Robin Georg |
1 |
416 |
Wed, 29 Jan 2003 03:00:00 GMT
rajesh5
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Instance name in NC Verilog? |
Srinivasan Venkataramana |
1 |
420 |
Tue, 28 Jan 2003 03:00:00 GMT
ghelbi
|
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iglasner@zumanetworks.com |
Marc Castell |
0 |
422 |
Tue, 28 Jan 2003 03:00:00 GMT
Marc Castell
|
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Parameter arrays, or equivalent? |
Paul Johnso |
10 |
415 |
Tue, 28 Jan 2003 03:00:00 GMT
Paul Johnso
|
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Expressions in a range? |
Selim Abou-Samr |
4 |
399 |
Mon, 27 Jan 2003 03:00:00 GMT
Michael McNamar
|
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PLL models |
s.. |
2 |
389 |
Mon, 27 Jan 2003 03:00:00 GMT
news.hinet.ne
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Format specifications in $display |
Edward Arthu |
0 |
427 |
Mon, 27 Jan 2003 03:00:00 GMT
Edward Arthu
|
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Opinions on a book? |
Brendan Lynske |
3 |
424 |
Mon, 27 Jan 2003 03:00:00 GMT
Jeremy S. Nichols, P
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I need to find instance name in NC Verilog |
ghelbi |
4 |
429 |
Mon, 27 Jan 2003 03:00:00 GMT
ghelbi
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String Concatenation |
Jason Rosinski - mr |
1 |
437 |
Sun, 26 Jan 2003 03:00:00 GMT
Paul Campbel
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