| Topics |
Author |
Replies |
Views |
Last post |
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digital phase-lock loop |
Gustav Jindr |
3 |
75 |
Tue, 01 Apr 2003 03:00:00 GMT
Tim Jayne
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Free Simulation Performance Seminar |
John Willoughb |
0 |
133 |
Mon, 31 Mar 2003 03:00:00 GMT
John Willoughb
|
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Need Verilog model of Xilinx PDA IIR/Biquad filter |
Tom |
0 |
135 |
Mon, 31 Mar 2003 03:00:00 GMT
Tom
|
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Width error |
tbryc.. |
2 |
139 |
Mon, 31 Mar 2003 03:00:00 GMT
Srinivasan Venkataramana
|
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using both edges of clock |
arvi.. |
2 |
135 |
Mon, 31 Mar 2003 03:00:00 GMT
Venkat Muralidha
|
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any timing diagram tool? |
Tony Zhan |
2 |
137 |
Mon, 31 Mar 2003 03:00:00 GMT
Bruc
|
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VCS->NC |
Edward Arthu |
11 |
138 |
Sun, 30 Mar 2003 03:00:00 GMT
Edward Arthu
|
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IP Cores and design for testability |
slwelsh2.. |
1 |
145 |
Sun, 30 Mar 2003 03:00:00 GMT
Patrick Schul
|
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Setup error |
tbryc.. |
1 |
147 |
Sat, 29 Mar 2003 03:00:00 GMT
Lars Rzymianowic
|
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Free EDA Software for sudents/universities |
Thomas Roc |
0 |
148 |
Sat, 29 Mar 2003 03:00:00 GMT
Thomas Roc
|
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Error during timing simulation |
tbryc.. |
1 |
151 |
Sat, 29 Mar 2003 03:00:00 GMT
Ken Ward - Hardwa
|
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synthesisable verilog? |
Nimish Kab |
11 |
70 |
Sat, 29 Mar 2003 03:00:00 GMT
Ulf Samuelsso
|
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Verilog netlist reader |
Ilya Grishashvil |
1 |
154 |
Fri, 28 Mar 2003 03:00:00 GMT
Bitter Spoc
|
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Verilog Model Compiler (VMC) |
jri.. |
0 |
155 |
Fri, 28 Mar 2003 03:00:00 GMT
jri..
|
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need verilog-In tool in PC |
news.hinet.ne |
0 |
158 |
Fri, 28 Mar 2003 03:00:00 GMT
news.hinet.ne
|
|
Long Island Verilog and VHDL people wanted!! |
Barry Schneide |
0 |
162 |
Thu, 27 Mar 2003 11:42:33 GMT
Barry Schneide
|
|
What kind of chips does verilog HDL targets ? |
Rod Di |
1 |
160 |
Thu, 27 Mar 2003 03:00:00 GMT
me..
|
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i2c core |
Greg Londo |
0 |
166 |
Wed, 26 Mar 2003 10:14:40 GMT
Greg Londo
|
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Verilog beginner trying to implement pipelining |
ab.. |
1 |
165 |
Wed, 26 Mar 2003 03:00:00 GMT
Jerry Englis
|
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Project Leader, Architecture Modeling |
brian13.. |
0 |
174 |
Tue, 25 Mar 2003 03:00:00 GMT
brian13..
|
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ANNOUNCE: C++ models for Verilog |
Adrian Lewi |
0 |
171 |
Tue, 25 Mar 2003 03:00:00 GMT
Adrian Lewi
|
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How to simulate in 2-value logic in ncsim |
Yang, Jerry [WDLN2:2W43:EXCH |
0 |
173 |
Tue, 25 Mar 2003 03:00:00 GMT
Yang, Jerry [WDLN2:2W43:EXCH
|
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New Yahoo club: EDA Wives and Girlfriends |
John Cool |
0 |
175 |
Tue, 25 Mar 2003 03:00:00 GMT
John Cool
|
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What happened to Wellspring Solutions, Inc. ? |
Rod Di |
2 |
173 |
Tue, 25 Mar 2003 03:00:00 GMT
Andy Botteril
|
|
any good DSP books? |
feng |
1 |
160 |
Tue, 25 Mar 2003 03:00:00 GMT
Netscape Use
|
|
Synthesizable I2C Core |
James W |
2 |
177 |
Mon, 24 Mar 2003 03:00:00 GMT
Edwin Grigoria
|
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how to model a FSM in behavioral? |
peng.. |
0 |
185 |
Sun, 23 Mar 2003 10:41:00 GMT
peng..
|
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feedback input with combinational logic! |
Jame |
4 |
188 |
Sun, 23 Mar 2003 03:00:00 GMT
pigSta
|
|
Hotwire into primitive |
doh.. |
2 |
175 |
Sun, 23 Mar 2003 03:00:00 GMT
Dave Ric
|
|
Free Gate-level verilog and SDF parser |
pinh.. |
1 |
166 |
Sun, 23 Mar 2003 03:00:00 GMT
pinh..
|
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c compiler for embedded CPU |
stefaan vanheesbek |
3 |
191 |
Thu, 20 Mar 2003 03:00:00 GMT
Cary Golterman
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