| Topics |
Author |
Replies |
Views |
Last post |
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Obnoxious noobie asks stoopid question |
Wesley Paris |
0 |
108 |
Wed, 30 Nov 2005 22:19:50 GMT
Wesley Paris
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parametrizable memory model |
New to Verilo |
4 |
102 |
Wed, 30 Nov 2005 01:28:29 GMT
Rob Dekke
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VHDL generate statement conversion |
New to Verilo |
1 |
112 |
Wed, 30 Nov 2005 00:58:56 GMT
Steven Sha
|
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Random Number Generator |
pran |
8 |
112 |
Tue, 29 Nov 2005 21:42:44 GMT
Rajesh Bawanku
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PDP11/40 Compatible CPU on an FPGA |
Naohiko Shimi |
1 |
75 |
Tue, 29 Nov 2005 15:45:42 GMT
Antti Luka
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Are there any free DSP core? |
Coole |
1 |
113 |
Tue, 29 Nov 2005 13:02:40 GMT
Gora
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How Verilog SHOULD handle this arithmetic operation? |
Jerr |
11 |
119 |
Tue, 29 Nov 2005 02:32:28 GMT
Steven Sha
|
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B17 SIMPLORER V6.0 (c) ANSOFT [2 CDs] - new ! |
astr.. |
0 |
121 |
Mon, 28 Nov 2005 22:13:25 GMT
astr..
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error compiling |
Mandilas Anton |
1 |
121 |
Mon, 28 Nov 2005 15:20:20 GMT
Alexander Gnus
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Formatting / Beautifying Verilog Code - Tools or Utilities Available ?? |
FriendlyGu |
3 |
123 |
Mon, 28 Nov 2005 08:42:20 GMT
Ira Baxte
|
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Verilog-2001 generate - do you need it? |
Jonathan Bromle |
5 |
125 |
Sun, 27 Nov 2005 23:17:53 GMT
Stephen William
|
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Fabs for students |
Davi |
6 |
111 |
Sun, 27 Nov 2005 18:52:33 GMT
fg
|
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Review of the new PSL Book by Ben Cohen |
Srinivasan Venkataramana |
2 |
132 |
Sun, 27 Nov 2005 15:18:27 GMT
ben coh
|
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Floating point. |
Brian Guralnic |
3 |
135 |
Sat, 26 Nov 2005 12:44:00 GMT
John Pento
|
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need VPI Verilog writer |
Henry Grishashvi |
0 |
136 |
Sat, 26 Nov 2005 04:52:35 GMT
Henry Grishashvi
|
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how to generate the clock |
Richard H |
2 |
137 |
Sat, 26 Nov 2005 01:06:18 GMT
Richard H
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How to pass a `define into a task |
Sundeep Chad |
0 |
141 |
Thu, 24 Nov 2005 12:28:19 GMT
Sundeep Chad
|
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OT: Jobs in Europe. |
Henr |
0 |
143 |
Thu, 24 Nov 2005 00:03:05 GMT
Henr
|
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how to use //synopsys full_case? |
zhangha |
11 |
146 |
Wed, 23 Nov 2005 16:41:39 GMT
Martin Euredjia
|
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Case Statement problem |
John Kol |
3 |
143 |
Wed, 23 Nov 2005 07:23:50 GMT
Steven Sha
|
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Assertion-based verification |
ben coh |
0 |
149 |
Tue, 22 Nov 2005 06:38:24 GMT
ben coh
|
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Accessing VHDL signals from Verilog test bench |
In Memory of tecNovi |
1 |
152 |
Mon, 21 Nov 2005 05:26:13 GMT
David Jon
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Post P&R Verilog/VHDL netlist |
Vishk |
2 |
137 |
Mon, 21 Nov 2005 02:58:04 GMT
Jaap Mo
|
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Build conf_test.exe |
Muhammad Kh |
2 |
157 |
Mon, 21 Nov 2005 01:37:47 GMT
Stuart Golodet
|
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Job Opportunity for HWE with Celoxica experience |
Jud |
0 |
157 |
Sun, 20 Nov 2005 23:14:20 GMT
Jud
|
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Code Coverage Tool |
Graem |
5 |
134 |
Sun, 20 Nov 2005 18:55:30 GMT
Chenbo Li
|
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Translating Verilog to VHDL |
Dani Kowalsk |
3 |
163 |
Sun, 20 Nov 2005 16:21:19 GMT
Srinivasan Venkataramana
|
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ANN: Confluence -> Python for Hardware Verification |
Tom Hawki |
6 |
164 |
Sun, 20 Nov 2005 02:15:13 GMT
John J. L
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HDLmaker update available |
B. Joshua Rose |
4 |
148 |
Sat, 19 Nov 2005 02:57:51 GMT
B. Joshua Rose
|
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iS THERE any Verilog source code for MPEG4/H.263/IDCT/HUFFMAN decoding? |
walal |
0 |
166 |
Sat, 19 Nov 2005 02:49:18 GMT
walal
|
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Should bit number of LHS and RHS in continuous assignment statement equal ? |
Bin |
5 |
171 |
Fri, 18 Nov 2005 20:24:31 GMT
Stephen William
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