| Topics |
Author |
Replies |
Views |
Last post |
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Simulating PALs in verilog? |
Paul Bouchi |
2 |
33 |
Sun, 11 Aug 1996 02:49:07 GMT
Stephen Te
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Are HDLs formal languages ? |
Budi Rahard |
43 |
51 |
Sat, 10 Aug 1996 23:16:27 GMT
John Willia
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REDUCING VERILOG MEMORY REQUIREMENTS |
Duke Xanthopoul |
6 |
48 |
Sat, 10 Aug 1996 09:15:34 GMT
Robert Brashea
|
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What is a good simulator? |
Mohan Pakkur |
0 |
45 |
Sat, 10 Aug 1996 01:34:46 GMT
Mohan Pakkur
|
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SIGDA Gopher Server Available |
Steve Frez |
3 |
24 |
Sat, 10 Aug 1996 01:21:47 GMT
D. Scott Baeder; x62
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REMINDER - Feb. 25/94 Deadline Approaching |
Janet Ti |
0 |
48 |
Wed, 07 Aug 1996 04:19:12 GMT
Janet Ti
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FAQ: Comp.lang.verilog Frequently Asked Questions (with answers) |
Steve Philli |
0 |
50 |
Tue, 06 Aug 1996 05:04:25 GMT
Steve Philli
|
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Tools for Verilog? |
Brent Webst |
0 |
53 |
Mon, 05 Aug 1996 05:14:25 GMT
Brent Webst
|
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Public-Domain Verilog Grammar |
Sashi V Obiliset |
0 |
55 |
Sun, 04 Aug 1996 23:09:25 GMT
Sashi V Obiliset
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TEST IGNORE |
Farrukh Zaf |
0 |
57 |
Sun, 04 Aug 1996 08:42:22 GMT
Farrukh Zaf
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HELP Veritime-Motive info needed |
W. Figurel |
0 |
60 |
Fri, 02 Aug 1996 19:33:48 GMT
W. Figurel
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verilog cpu |
Jay Bro |
0 |
64 |
Tue, 30 Jul 1996 09:16:35 GMT
Jay Bro
|
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Effective Programmers (was Re: Area in gates on Synopsys) |
Mike Ekberg, Cirrus Logic.UserInterface - MS 531B |
0 |
66 |
Tue, 30 Jul 1996 08:29:29 GMT
Mike Ekberg, Cirrus Logic.UserInterface - MS 531B
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Synthesizable Verilog Models |
Andrew Fraz |
0 |
69 |
Tue, 30 Jul 1996 02:31:23 GMT
Andrew Fraz
|
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big designs? |
Stephen Broo |
0 |
71 |
Mon, 29 Jul 1996 21:25:44 GMT
Stephen Broo
|
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PD version of the ELLA HDL |
David Taylo |
0 |
73 |
Mon, 29 Jul 1996 17:13:30 GMT
David Taylo
|
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Verilog-HDL Applications Engineer / Los Altos, CA |
Joel Past |
0 |
75 |
Mon, 29 Jul 1996 12:17:52 GMT
Joel Past
|
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data management |
Van der Kloot, Hardwa |
0 |
77 |
Mon, 29 Jul 1996 05:52:21 GMT
Van der Kloot, Hardwa
|
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IEEE Workshop on Custom Computing Machines |
Duncan A. Bue |
0 |
79 |
Mon, 29 Jul 1996 02:17:58 GMT
Duncan A. Bue
|
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Area in gates on Synopsys |
John Cool |
5 |
75 |
Sun, 28 Jul 1996 19:21:19 GMT
John Willia
|
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Multiple Module instantiation |
brian dav |
16 |
70 |
Sun, 28 Jul 1996 07:25:11 GMT
leung_stev
|
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VHDL vs. Verilog |
John Sanguinet |
13 |
75 |
Sun, 28 Jul 1996 02:16:49 GMT
John Willia
|
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Verilog coding question - connects |
Michael T.Y. McNama |
5 |
82 |
Sun, 28 Jul 1996 01:11:19 GMT
Michael T.Y. McNama
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Handling X delays in verilog |
Rama Kowsalya :: N |
2 |
77 |
Sat, 27 Jul 1996 18:20:07 GMT
Robert Brashea
|
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FAQ: Comp.lang.verilog Frequently Asked Questions (with answers) |
Steve Philli |
0 |
86 |
Sat, 27 Jul 1996 16:22:21 GMT
Steve Philli
|
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Veriwell/Mac |
Swaminatha V. Gurudev |
0 |
88 |
Fri, 26 Jul 1996 01:23:28 GMT
Swaminatha V. Gurudev
|
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Job opportunity in VHDL Simulation Models |
Escalade Co |
0 |
90 |
Thu, 25 Jul 1996 05:03:51 GMT
Escalade Co
|
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Area in gates on Synopsys |
John Willia |
0 |
92 |
Wed, 24 Jul 1996 17:06:02 GMT
John Willia
|
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Experience moving netlists: Synopsys to GDT |
Greg Wa |
0 |
96 |
Sun, 21 Jul 1996 22:12:43 GMT
Greg Wa
|
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Verilog "lint" |
Marc Clar |
3 |
98 |
Sun, 21 Jul 1996 07:48:45 GMT
John Hagerm
|
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Verilog equivalent of VHDL 'for...generate'? |
Tommy Kel |
1 |
80 |
Sat, 20 Jul 1996 19:47:28 GMT
John Bus
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