| Topics |
Author |
Replies |
Views |
Last post |
 |
MARKET SURVEY |
sngme.. |
0 |
524 |
Sun, 06 Oct 1996 10:49:58 GMT
sngme..
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triggering off of CMOS pads problem |
Paul Gerla |
4 |
524 |
Sun, 06 Oct 1996 02:06:59 GMT
Clifford E. Cummin
|
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Defining test-case complexity [Q] |
Mark Sh |
1 |
525 |
Sun, 06 Oct 1996 00:47:02 GMT
John Willia
|
|
FAQ: Comp.lang.verilog Frequently Asked Questions (with answers) |
Steve Philli |
0 |
528 |
Sat, 05 Oct 1996 23:21:54 GMT
Steve Philli
|
|
Book |
Jeffrey A Echtenka |
0 |
530 |
Sat, 05 Oct 1996 22:01:56 GMT
Jeffrey A Echtenka
|
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code reuse |
Don Mil |
4 |
524 |
Sat, 05 Oct 1996 22:00:06 GMT
R.S. ChandraSekar
|
|
Is always really ALWAYS? |
Aron Hein |
0 |
533 |
Sat, 05 Oct 1996 02:57:56 GMT
Aron Hein
|
|
Attention Verilog consultants |
Sutherland HDL Consu |
0 |
535 |
Sat, 05 Oct 1996 02:54:29 GMT
Sutherland HDL Consu
|
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Delayed IF question. |
Aron Hein |
7 |
529 |
Sat, 05 Oct 1996 02:25:54 GMT
Michael Lodm
|
|
Efficiency Question |
Mark Lefev |
1 |
533 |
Thu, 03 Oct 1996 01:50:38 GMT
John Willia
|
|
Why Verilog |
Jos De Laender - SH144 - X74 |
2 |
541 |
Tue, 01 Oct 1996 21:46:06 GMT
Sutherland HDL Consu
|
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FAQ: Comp.lang.verilog Frequently Asked Questions (with answers) |
Steve Philli |
0 |
541 |
Mon, 30 Sep 1996 22:24:35 GMT
Steve Philli
|
|
M-x compile for verilog |
Tommy Kel |
1 |
545 |
Sun, 29 Sep 1996 21:01:59 GMT
Tommy Kel
|
|
UDP help requested |
Paul L |
3 |
549 |
Sat, 28 Sep 1996 05:35:41 GMT
John Willia
|
|
Verilog training courses? |
Carl Pond |
0 |
548 |
Tue, 24 Sep 1996 23:17:11 GMT
Carl Pond
|
|
Waveform Display Systems |
SteveP12 |
8 |
554 |
Mon, 23 Sep 1996 02:10:03 GMT
Paul Campbe
|
|
CFP: ASPDAC'95, CHDL'95, VLSI'95 |
Youn-Long L |
0 |
552 |
Sun, 22 Sep 1996 20:58:12 GMT
Youn-Long L
|
|
ECAD Software |
Colley M |
0 |
554 |
Sun, 22 Sep 1996 19:42:57 GMT
Colley M
|
|
FAQ: Comp.lang.verilog Frequently Asked Questions (with answers) |
Steve Philli |
0 |
556 |
Sun, 22 Sep 1996 00:27:38 GMT
Steve Philli
|
|
IEEE Working Group Minutes |
Elliot Medni |
0 |
558 |
Sat, 21 Sep 1996 07:23:15 GMT
Elliot Medni
|
|
I need a Verilog (FREE!) manual (for beginner) |
Kenneth Coop |
0 |
562 |
Wed, 18 Sep 1996 08:41:01 GMT
Kenneth Coop
|
|
I need a FREE !!! manual(good one!) |
Kenneth Coop |
0 |
564 |
Wed, 18 Sep 1996 08:36:01 GMT
Kenneth Coop
|
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Code for simulation of systolic array |
Donald Uwemedimo Eko |
0 |
566 |
Tue, 17 Sep 1996 02:29:51 GMT
Donald Uwemedimo Eko
|
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Mismatch between timing violations and vcd files using SDF. |
Gavin Brebn |
1 |
565 |
Mon, 16 Sep 1996 18:08:48 GMT
Robert Brashea
|
|
From the News Wire |
Michael T.Y. McNama |
0 |
569 |
Mon, 16 Sep 1996 04:37:53 GMT
Michael T.Y. McNama
|
|
NIM: Cdn. Workshop on Field-Programmable Devices |
Janet Ti |
0 |
120 |
Sat, 14 Sep 1996 03:48:20 GMT
Janet Ti
|
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Verilog -> VHDL |
Jos De Laender - SH144 - X74 |
2 |
568 |
Sat, 14 Sep 1996 00:24:39 GMT
Pete Jam
|
|
Help needed |
Rajeswaran Viswanath |
1 |
563 |
Fri, 13 Sep 1996 12:49:24 GMT
Narendra Ja
|
|
Need email address for benchmarks from IVC conference |
Steve Mey |
1 |
123 |
Sun, 08 Sep 1996 18:21:52 GMT
Joseph Skudlar
|
|
Use of cwaves |
Fazil Osm |
3 |
582 |
Sun, 08 Sep 1996 08:16:47 GMT
Clifford E Cummin
|
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ASIC Job, New Grad, RTP,NC |
John Hawkins P7 |
0 |
581 |
Sun, 08 Sep 1996 07:09:07 GMT
John Hawkins P7
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