| Topics |
Author |
Replies |
Views |
Last post |
 |
parameter redefinition |
Terence Gilhu |
9 |
272 |
Mon, 30 Dec 1996 06:05:56 GMT
Dave Ri
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Two-dimensional arrays in verilog-are they synthesizable? |
Shoba Krishn |
0 |
285 |
Sun, 29 Dec 1996 02:11:19 GMT
Shoba Krishn
|
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SDF file parser? |
Jeffrey L. Be |
1 |
279 |
Sat, 28 Dec 1996 23:19:58 GMT
Ian Dobins
|
|
Verilog synthesis tools |
Jose Vicente Lidon Rog |
4 |
269 |
Sat, 28 Dec 1996 20:39:09 GMT
RSMoo
|
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How can I obtain OVI's Open HDL or any Verilog synth tool? |
Sitaram Yadaval |
3 |
286 |
Fri, 27 Dec 1996 02:20:03 GMT
Jim Ste
|
|
Verilog for complex PLD's |
John Cool |
4 |
292 |
Wed, 25 Dec 1996 07:34:28 GMT
Brad Gart
|
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Segmenting Test Vectors |
Paul Wareh |
0 |
294 |
Wed, 25 Dec 1996 03:58:10 GMT
Paul Wareh
|
|
URGENT HELP REQUESTED: back annotation |
Mark Lefev |
0 |
298 |
Tue, 24 Dec 1996 10:21:11 GMT
Mark Lefev
|
|
Simulator Front Ends |
Elliott.N |
1 |
296 |
Mon, 23 Dec 1996 23:05:46 GMT
John Willia
|
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What does "&&&" mean? |
Tim Stercz |
1 |
302 |
Mon, 23 Dec 1996 22:26:04 GMT
Craig Botk
|
|
Macro processor or meta-language |
Paul Gerla |
1 |
304 |
Mon, 23 Dec 1996 07:22:34 GMT
John Willia
|
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parity generator needed |
Gary Kidwe |
2 |
299 |
Sun, 22 Dec 1996 23:30:02 GMT
Michael J. Hellm
|
|
Ampersands used in Verilog language |
Wayne Be |
1 |
303 |
Sun, 22 Dec 1996 03:08:45 GMT
Michael T.Y. McNama
|
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OVI PLI Interface Mechanism compliance |
Christopher G. Tscharn |
6 |
308 |
Sat, 21 Dec 1996 22:41:34 GMT
Clifford E. Cummin
|
|
Huffman codec description wanted |
Javier MART |
0 |
309 |
Sat, 21 Dec 1996 20:15:29 GMT
Javier MART
|
|
Gate question |
Mark Lefev |
0 |
315 |
Wed, 18 Dec 1996 02:20:24 GMT
Mark Lefev
|
|
Verilog and VHDL |
Tume Rom |
0 |
317 |
Tue, 17 Dec 1996 15:00:28 GMT
Tume Rom
|
|
Source for ISA bus emula? |
Tom Bak |
2 |
319 |
Tue, 17 Dec 1996 02:36:34 GMT
Gunes Ayb
|
|
Verilog test suite |
Daniel Chapi |
0 |
323 |
Mon, 16 Dec 1996 07:03:42 GMT
Daniel Chapi
|
|
Signed multiplication |
Lee Bradsh |
2 |
325 |
Mon, 16 Dec 1996 04:42:13 GMT
Rajesh Pat
|
|
Employment Opportunity - ASIC/Simulation Engineers |
Compaq Computer Cor |
0 |
327 |
Sun, 15 Dec 1996 21:19:19 GMT
Compaq Computer Cor
|
|
Verilog regression suite |
Hyun-Taek Chang [4 |
0 |
329 |
Sun, 15 Dec 1996 04:56:16 GMT
Hyun-Taek Chang [4
|
|
emacs mode for verilog |
Khozema Khamba |
1 |
332 |
Sat, 14 Dec 1996 06:11:01 GMT
michael f sulliv
|
|
models of serial EEPROMS needed |
Gary Kidwe |
0 |
335 |
Sat, 14 Dec 1996 02:35:07 GMT
Gary Kidwe
|
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What graphical state machine tools are people using? |
Chuck Paglic |
0 |
335 |
Fri, 13 Dec 1996 23:16:52 GMT
Chuck Paglic
|
|
Intel CPU Verilog Models |
Tomoo Taguc |
0 |
339 |
Fri, 13 Dec 1996 23:02:08 GMT
Tomoo Taguc
|
|
records? arrays? generate? |
THOMAS L DRABENSTO |
2 |
338 |
Fri, 13 Dec 1996 20:38:13 GMT
Stuart Sutherla
|
|
Call for Papers |
Jacques Rouilla |
0 |
311 |
Fri, 20 Dec 1996 23:25:10 GMT
Jacques Rouilla
|
|
PARTIAL SCAN BOOKLET |
Alex Mic |
0 |
319 |
Tue, 17 Dec 1996 09:11:22 GMT
Alex Mic
|
|
Input Data File |
Denny S |
3 |
322 |
Mon, 16 Dec 1996 01:23:48 GMT
Robert Brashea
|
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