| Topics |
Author |
Replies |
Views |
Last post |
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JOB POSTING: Project Lead - Distributed Verilog Simulation, CA |
Ramesh Narayanaswa |
0 |
224 |
Wed, 15 Jan 1997 10:01:07 GMT
Ramesh Narayanaswa
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C routines to Verilog |
Aurobindo Dasgup |
1 |
213 |
Wed, 15 Jan 1997 02:46:11 GMT
Masaharu Go
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12th ACM/IEEE International Conference on Computer-Aided Design |
Gaetano Borriel |
2 |
185 |
Tue, 14 Jan 1997 07:34:37 GMT
Jan Otterste
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Reading inputs from a file |
Niranjan Coor |
3 |
225 |
Mon, 13 Jan 1997 04:57:17 GMT
Steve Mey
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Job Opening - Technical Sales Representative |
Steve Pollo |
0 |
231 |
Mon, 13 Jan 1997 01:05:19 GMT
Steve Pollo
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Parallel or Sequential That is The Question! |
Phil Cupr |
2 |
233 |
Sun, 12 Jan 1997 23:29:15 GMT
Gord Wait S-MOS Systems Vancouver Design Cent
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To Stuart Sutherland... |
MarkPa |
0 |
236 |
Sat, 11 Jan 1997 23:58:08 GMT
MarkPa
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How to pass a string from PLI to verilog/vcs |
yehoshua shosh |
0 |
239 |
Sat, 11 Jan 1997 18:49:27 GMT
yehoshua shosh
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transputer model needed |
K Y |
0 |
239 |
Sat, 11 Jan 1997 18:43:16 GMT
K Y
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Language(s) for Microprograms ? |
Sitaram Yadaval |
14 |
219 |
Fri, 10 Jan 1997 16:11:54 GMT
DStri
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Parameter redef's |
Jonathan L. DeKo |
0 |
248 |
Fri, 10 Jan 1997 13:13:29 GMT
Jonathan L. DeKo
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Verilog Class |
Ken Goldm |
1 |
251 |
Tue, 07 Jan 1997 23:30:19 GMT
Kartik Subbar
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How to pass a string from PLI to verilog/vcs |
yehoshua shosh |
0 |
252 |
Tue, 07 Jan 1997 21:37:06 GMT
yehoshua shosh
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Verilog resistor models |
Larry Atkins |
0 |
250 |
Tue, 07 Jan 1997 21:28:17 GMT
Larry Atkins
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Synthesizing the initial statement |
Hugh Barra |
0 |
255 |
Tue, 07 Jan 1997 16:12:03 GMT
Hugh Barra
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inout ports |
Matt DeBergal |
5 |
255 |
Tue, 07 Jan 1997 03:09:11 GMT
Dave Ri
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How can I build a model of a resistor? |
Lauren Bak |
0 |
258 |
Tue, 07 Jan 1997 00:48:01 GMT
Lauren Bak
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Creating a resistor model for system level synthesis |
Lauren Bak |
11 |
254 |
Sun, 05 Jan 1997 05:59:51 GMT
Kartik Subbar
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Verilog simulation model for TMS320C51 |
Hsin-Huei L |
0 |
262 |
Sun, 05 Jan 1997 02:20:23 GMT
Hsin-Huei L
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Redefining specparams per instance |
Mohrgan Pratt |
2 |
244 |
Sat, 04 Jan 1997 22:44:14 GMT
Steven Greenbe
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Timescale resolution |
PC_us |
4 |
245 |
Sat, 04 Jan 1997 10:35:23 GMT
Dave Ri
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Verilog clone |
Jae C |
0 |
267 |
Wed, 01 Jan 1997 07:20:54 GMT
Jae C
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parameter redefinition II |
Terence Gilhu |
1 |
268 |
Wed, 01 Jan 1997 01:17:36 GMT
Michael T.Y. McNama
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Prioritizing transitions in UDPs |
Shankar Hemma |
3 |
262 |
Wed, 01 Jan 1997 00:24:22 GMT
Dave Ri
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always statemnt's order in same simulation time |
Akihiro Takamu |
7 |
274 |
Tue, 31 Dec 1996 16:25:11 GMT
Janick Berger
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Contact for Ikos?? |
Keith Lawren |
0 |
275 |
Mon, 30 Dec 1996 23:24:59 GMT
Keith Lawren
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Contact for CAD Artisans |
Keith Lawren |
0 |
277 |
Mon, 30 Dec 1996 23:22:41 GMT
Keith Lawren
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xnf to Verilog translator |
Jae C |
0 |
275 |
Mon, 30 Dec 1996 23:10:28 GMT
Jae C
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SNUG Europe Advanced Notice & CFP |
John Cool |
0 |
280 |
Mon, 30 Dec 1996 16:03:09 GMT
John Cool
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parameter redefinition |
Terence Gilhu |
9 |
272 |
Mon, 30 Dec 1996 06:05:56 GMT
Dave Ri
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