| Topics |
Author |
Replies |
Views |
Last post |
 |
FSM and Wait States |
odasa |
4 |
506 |
Sat, 26 Feb 2005 01:41:29 GMT
Utku Ozca
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DPLL verilog |
Frank Zhifeng Yua |
3 |
576 |
Fri, 25 Feb 2005 22:27:56 GMT
swei
|
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a problem about cadence LDV33 |
Martyn Pollar |
0 |
576 |
Fri, 25 Feb 2005 22:13:22 GMT
Martyn Pollar
|
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Free Waveform Viewer for the Macintosh? (OSX) |
David Bet |
3 |
0 |
Fri, 25 Feb 2005 02:08:57 GMT
Eri
|
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SDF annotation using ncelab for encryption IP net [2]? |
onepow |
0 |
583 |
Tue, 22 Feb 2005 10:40:13 GMT
onepow
|
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How can I use the compile directive "`uselib" in ISE 4.2? |
Yx Jian |
0 |
586 |
Tue, 22 Feb 2005 08:39:42 GMT
Yx Jian
|
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LRM for Verilog 2001 and System Verilog |
ehml |
1 |
589 |
Tue, 22 Feb 2005 00:14:29 GMT
Dave Ric
|
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How I can know real time of modeling(simulating) uses commands Verilog? (not modeling time) |
vladim |
2 |
593 |
Mon, 21 Feb 2005 00:08:13 GMT
ehml
|
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Verilog IP cores on demand |
Tina Falkenber |
0 |
594 |
Sun, 20 Feb 2005 11:41:35 GMT
Tina Falkenber
|
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Ethernet controller |
Nira |
4 |
596 |
Fri, 18 Feb 2005 04:06:30 GMT
Nira
|
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chip substrate design verification |
Nahum Barn |
0 |
599 |
Thu, 17 Feb 2005 23:26:17 GMT
Nahum Barn
|
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FAQ? |
Ari Ranku |
1 |
2 |
Wed, 16 Feb 2005 22:40:55 GMT
Swapnajit Mitt
|
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Delays on Bidirectional Signals |
Jason Graalu |
0 |
3 |
Wed, 16 Feb 2005 00:15:02 GMT
Jason Graalu
|
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PROTEL ALTIUM DESIGN EXPLORER V 7.0.737 WinNT2000XP |
LET |
0 |
6 |
Tue, 15 Feb 2005 21:05:18 GMT
LET
|
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about reset |
Apol |
3 |
589 |
Tue, 15 Feb 2005 09:52:22 GMT
Zhou Cha
|
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Question: named port assignment |
Zhiyong Wan |
2 |
9 |
Tue, 15 Feb 2005 08:36:34 GMT
John_
|
|
prbs |
Jacob El |
1 |
12 |
Tue, 15 Feb 2005 01:29:01 GMT
John_
|
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If "a net can not hold a value" then why does this work? |
Tom |
4 |
9 |
Mon, 14 Feb 2005 06:31:29 GMT
glen herrmannsfeld
|
|
typical verilog questions |
Cliff Cummin |
0 |
16 |
Mon, 14 Feb 2005 04:20:05 GMT
Cliff Cummin
|
|
ITU-BT.601 to ITU-BT.656 video conversion? |
Mark |
0 |
18 |
Sun, 13 Feb 2005 22:52:20 GMT
Mark
|
|
Verilog using LPM standards |
ah |
3 |
9 |
Sun, 13 Feb 2005 22:33:22 GMT
Swapnajit Mitt
|
|
Back Anotation |
vino |
2 |
20 |
Sun, 13 Feb 2005 19:33:03 GMT
Swapnajit Mitt
|
|
Verilog Distributed Simulation Tool |
Yuri Roytm |
1 |
25 |
Sat, 12 Feb 2005 03:48:04 GMT
Petter Gusta
|
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logging $system output |
Chris Brig |
4 |
28 |
Fri, 11 Feb 2005 03:20:38 GMT
Chris Brig
|
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Scripting Langauges |
Robert Schopmey |
3 |
17 |
Thu, 10 Feb 2005 05:10:40 GMT
Phil Toms
|
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MCU |
Ensoul Che |
1 |
582 |
Tue, 22 Feb 2005 10:40:32 GMT
Jon Benisto
|
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Using Wilson Snyder's Verilog-Perl with NC Verilog |
David Zalati |
2 |
529 |
Tue, 22 Feb 2005 08:50:01 GMT
Nahum Barn
|
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Resume: HW Verification Consultant (Specman) |
Chris Star |
0 |
12 |
Tue, 15 Feb 2005 01:42:30 GMT
Chris Star
|
|
Fine Wine and Analog Design |
Howard Frank |
0 |
29 |
Thu, 10 Feb 2005 03:39:56 GMT
Howard Frank
|
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Resume: HW Verification Consultant (Specman) |
Chris Star |
0 |
579 |
Tue, 22 Feb 2005 20:50:12 GMT
Chris Star
|
|
Any interest in a Specman newsgroup |
M Pedl |
2 |
532 |
Sun, 13 Feb 2005 20:27:08 GMT
news
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