| Topics |
Author |
Replies |
Views |
Last post |
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PLI 2.0 and Call Back (Help!) |
Palmo Ricchiut |
1 |
47 |
Fri, 14 May 1999 03:00:00 GMT
Kim Galeazz
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Who uses the Verilog PLI? |
Kurt Schwart |
3 |
188 |
Fri, 14 May 1999 03:00:00 GMT
John Cool
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synthesis strategy |
Rainer Theue |
3 |
190 |
Fri, 14 May 1999 03:00:00 GMT
Prasad Paranjp
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How do I read huge trace-files into Verilog HDL? |
Tommi Jokine |
1 |
53 |
Thu, 13 May 1999 03:00:00 GMT
Jason Campbel
|
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Just try this, it will work |
Stephen Boltinghou |
0 |
54 |
Wed, 12 May 1999 03:00:00 GMT
Stephen Boltinghou
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useful links |
rainer |
3 |
56 |
Mon, 10 May 1999 03:00:00 GMT
Gerard M Blai
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Verilog to C for Behavioral Verilog |
Mark E Kautzma |
0 |
59 |
Mon, 10 May 1999 03:00:00 GMT
Mark E Kautzma
|
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CFP: FCCM'97 IEEE Symp on Custom Computing Machines |
Jeffrey Arno |
0 |
196 |
Sun, 09 May 1999 03:00:00 GMT
Jeffrey Arno
|
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POSITION: VHDL ASIC Designer |
alain arna |
0 |
198 |
Sun, 09 May 1999 03:00:00 GMT
alain arna
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Can VHDL do test benches as elegantly as Verilog. |
Ian Lan |
1 |
61 |
Sun, 09 May 1999 03:00:00 GMT
Jim Lewi
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FPGA Gate Counts: No Truth in Advertising |
da.. |
5 |
62 |
Sun, 09 May 1999 03:00:00 GMT
Peter Alfk
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>>> ARE YOU READY FOR LOVE? <<< |
love |
0 |
342 |
Sat, 08 May 1999 03:00:00 GMT
love
|
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***CONTINUATION ENGINEERS, APPLE COMPUTER, INC.*** |
Cheryl Ericks |
0 |
344 |
Sat, 08 May 1999 03:00:00 GMT
Cheryl Ericks
|
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vl2mv |
Roddy Jin |
0 |
50 |
Sat, 08 May 1999 03:00:00 GMT
Roddy Jin
|
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Re : User Defined Primitives |
Vivek Sagde |
0 |
52 |
Sat, 08 May 1999 03:00:00 GMT
Vivek Sagde
|
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Usage of parameters in verilog modules |
Sharon Ben-Davi |
2 |
209 |
Fri, 07 May 1999 03:00:00 GMT
Gerard M Blai
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VHDL code editor for Windows NT. |
Crystal Harve |
3 |
65 |
Thu, 06 May 1999 03:00:00 GMT
Kevin Steel
|
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CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA |
1997 International Symposium on Physical Desi |
0 |
351 |
Thu, 06 May 1999 03:00:00 GMT
1997 International Symposium on Physical Desi
|
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SONET/SDH Test Bench Needed |
Carol Sale |
0 |
353 |
Mon, 03 May 1999 03:00:00 GMT
Carol Sale
|
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The best timing diagram editor/simulator? |
Lindo St Ange |
8 |
220 |
Mon, 03 May 1999 03:00:00 GMT
Oleg Milte
|
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correct simulation results? |
Patrick VanHoomiss |
1 |
358 |
Sun, 02 May 1999 03:00:00 GMT
m..
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EDIF netlist file to BLIF netlist file.. |
Ketan Poladi |
0 |
359 |
Sun, 02 May 1999 03:00:00 GMT
Ketan Poladi
|
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(no subject) |
Vivek Sagde |
2 |
363 |
Sun, 02 May 1999 03:00:00 GMT
Vivek Sagde
|
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Request for LRM |
David Elli |
0 |
362 |
Sat, 01 May 1999 03:00:00 GMT
David Elli
|
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Reconfig interactive report |
sba.. |
0 |
364 |
Sat, 01 May 1999 03:00:00 GMT
sba..
|
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rules on transferring software license |
Joe L. Rainbol |
5 |
225 |
Sat, 01 May 1999 03:00:00 GMT
Steve Po
|
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Session 3: Gateway to Verilog |
Gerard M Blai |
0 |
367 |
Fri, 30 Apr 1999 03:00:00 GMT
Gerard M Blai
|
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Verilog Hackers - Sequential UDP clarification |
Dave Ric |
0 |
370 |
Fri, 30 Apr 1999 03:00:00 GMT
Dave Ric
|
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'z' buffer w/ specify block?!? |
Todd Wa |
0 |
372 |
Fri, 30 Apr 1999 03:00:00 GMT
Todd Wa
|
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Verilog Language Upgrade |
taniwh |
0 |
215 |
Sun, 02 May 1999 03:00:00 GMT
taniwh
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