| Topics |
Author |
Replies |
Views |
Last post |
 |
Clock singals |
Mandilas Anton |
1 |
48 |
Thu, 15 Dec 2005 15:45:46 GMT
Uwe Bonne
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Could somebody introduce me some books on verilog and Synopsys DC? |
Peng |
4 |
47 |
Thu, 15 Dec 2005 10:07:56 GMT
Jo
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Need some models and tests coded soon |
J F |
1 |
48 |
Wed, 14 Dec 2005 13:22:01 GMT
Rajkum
|
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combinational divider |
hswnet |
1 |
57 |
Tue, 13 Dec 2005 20:36:47 GMT
B. Joshua Rose
|
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explicit time units and timescale restore in verilog |
Anatoly Gelma |
4 |
54 |
Tue, 13 Dec 2005 13:53:38 GMT
Anatoly Gelma
|
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Verilog Assertion Problem |
New to Verilo |
2 |
56 |
Tue, 13 Dec 2005 10:38:29 GMT
Ajeetha Kuma
|
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verilog instance name length |
W |
1 |
58 |
Tue, 13 Dec 2005 09:18:44 GMT
DSLuse
|
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Operator Overloading in Verilog |
Tze Yi Yeo |
2 |
59 |
Tue, 13 Dec 2005 07:53:12 GMT
Ajeetha Kuma
|
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verilog equivalent to weak high in vhdl |
srinivas tura |
1 |
63 |
Mon, 12 Dec 2005 20:56:32 GMT
Uwe Bonne
|
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UART Implementation |
Anand P Paralka |
2 |
48 |
Mon, 12 Dec 2005 20:36:26 GMT
Rudolf Usselma
|
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audio video application graphs |
srin |
0 |
66 |
Mon, 12 Dec 2005 15:14:34 GMT
srin
|
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encrypted sdf's |
Paul Richardso |
0 |
68 |
Mon, 12 Dec 2005 01:27:44 GMT
Paul Richardso
|
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Fully defined case statement? |
Allen S |
3 |
63 |
Mon, 12 Dec 2005 01:01:28 GMT
Allen S
|
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LABVIEW V7.0 [2 CDs], SABER DESIGNER V2003.6 - SYNOPSYS - new ! |
vv.. |
0 |
71 |
Sun, 11 Dec 2005 18:12:30 GMT
vv..
|
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Linting tool for verilog |
Amee |
1 |
70 |
Sun, 11 Dec 2005 16:28:43 GMT
Srinivasan Venkataramana
|
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free Verilog-A parser? |
wanb |
1 |
78 |
Sat, 10 Dec 2005 08:04:45 GMT
Rob Dekke
|
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Q: regarding I2C protocols |
y_p_ |
18 |
93 |
Sat, 10 Dec 2005 01:37:40 GMT
kryten_droi
|
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FSM problem |
Martin Euredjia |
9 |
64 |
Thu, 08 Dec 2005 07:52:56 GMT
Saja
|
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Verilog-2001 tool support: spotty at best? |
don |
3 |
82 |
Thu, 08 Dec 2005 00:33:16 GMT
oiwo
|
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Modeling Data Bus at run time in Verilog Test Fixture |
Joel Winars |
1 |
85 |
Wed, 07 Dec 2005 03:33:55 GMT
Muzaffer Ka
|
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Strange behaviour in initial block |
K |
5 |
92 |
Tue, 06 Dec 2005 17:45:53 GMT
Stephen William
|
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read from files with verilog A |
Lars Schube |
1 |
94 |
Mon, 05 Dec 2005 16:59:58 GMT
Lars Schube
|
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gtkwave with Icarus verilog |
And |
4 |
96 |
Mon, 05 Dec 2005 15:12:33 GMT
And
|
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Delay amount and pulsewidth |
Alan De |
1 |
95 |
Mon, 05 Dec 2005 11:16:03 GMT
Steven Sha
|
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The Verilog PLL model? |
walt |
2 |
80 |
Sun, 04 Dec 2005 23:44:59 GMT
Ashr
|
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Keep The SEGWAY Off Our Sidewalks & Streets! ------ #randum |
Kiera |
0 |
103 |
Fri, 02 Dec 2005 17:31:47 GMT
Kiera
|
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Reading a netlist |
Amee |
0 |
105 |
Fri, 02 Dec 2005 16:24:03 GMT
Amee
|
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Obnoxious noobie asks stoopid question |
Wesley Paris |
0 |
108 |
Wed, 30 Nov 2005 22:19:50 GMT
Wesley Paris
|
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trouble with path delays |
Dave Ardr |
1 |
81 |
Wed, 07 Dec 2005 03:25:07 GMT
Marc
|
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mathematical functions in Verilog |
New to Verilo |
3 |
103 |
Sat, 03 Dec 2005 07:25:42 GMT
Swapnajit Mitt
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