| Topics |
Author |
Replies |
Views |
Last post |
 |
comparison with xxxx |
Shardendu Pande |
7 |
370 |
Tue, 15 Jan 2002 03:00:00 GMT
Zyad Achou
|
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Scripts for Hierarchy generation |
Alex Cefal |
1 |
371 |
Tue, 15 Jan 2002 03:00:00 GMT
Puneet Goe
|
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How do I display the system date? |
Robert Baile |
2 |
405 |
Mon, 14 Jan 2002 03:00:00 GMT
hassa
|
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$display |
Tomasz Brychc |
2 |
407 |
Mon, 14 Jan 2002 03:00:00 GMT
hassa
|
|
ARM7 behavioral modeling |
?-?μ? |
1 |
413 |
Mon, 14 Jan 2002 03:00:00 GMT
Ulf Samuelsso
|
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GENERATE? |
William LenihanIi |
1 |
415 |
Mon, 14 Jan 2002 03:00:00 GMT
Swapnajit Mittr
|
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Desiging FIFO in Verilog |
Tim Webste |
0 |
416 |
Sun, 13 Jan 2002 03:00:00 GMT
Tim Webste
|
|
i thought this was a technical newsgroup ... |
Andrew Peeble |
1 |
420 |
Sun, 13 Jan 2002 03:00:00 GMT
Baris Akso
|
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why escape characters!!! |
DurgaPrasad. |
4 |
411 |
Sun, 13 Jan 2002 03:00:00 GMT
Edward Arthu
|
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Verilog and Modelsim |
Reza Bohran |
4 |
402 |
Sat, 12 Jan 2002 03:00:00 GMT
Brett Clin
|
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Synthesized testbenches |
Shardendu Pande |
7 |
407 |
Sat, 12 Jan 2002 03:00:00 GMT
rajes..
|
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FIFO in verilog? |
Gregory V. Larche |
0 |
424 |
Sat, 12 Jan 2002 03:00:00 GMT
Gregory V. Larche
|
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This week's CODING TIP .... |
Sashi Obilisett |
0 |
429 |
Fri, 11 Jan 2002 03:00:00 GMT
Sashi Obilisett
|
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looking for: vcd -> hp83000 |
apeeb.. |
0 |
433 |
Wed, 09 Jan 2002 03:00:00 GMT
apeeb..
|
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loss clock |
EXCHANGE:SKY:1V |
2 |
434 |
Tue, 08 Jan 2002 03:00:00 GMT
parvathy_..
|
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Bus functional model for ARM7 |
Hans Bet |
1 |
439 |
Tue, 08 Jan 2002 03:00:00 GMT
Hans Bet
|
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Mixed Signal Design Engineers Wanted |
Margaret Daile |
0 |
440 |
Tue, 08 Jan 2002 03:00:00 GMT
Margaret Daile
|
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sdf files |
pan.. |
1 |
443 |
Mon, 07 Jan 2002 03:00:00 GMT
Matt Gutha
|
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Workstation with Synopsys license server |
Friedhelm Rü |
2 |
443 |
Mon, 07 Jan 2002 03:00:00 GMT
Paul Hand
|
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Knowing when Verilog is exiting |
Doug Hillme |
3 |
442 |
Mon, 07 Jan 2002 03:00:00 GMT
Thomas A. Coon
|
|
Readmem warning |
pan.. |
2 |
445 |
Sat, 05 Jan 2002 03:00:00 GMT
Don Re
|
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License sharing for synopsys/cadence/modeltech |
chipfact.. |
10 |
460 |
Fri, 04 Jan 2002 03:00:00 GMT
Peter Beukelma
|
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This week's HDL Coding Tip |
Sashi Obilisett |
0 |
453 |
Fri, 04 Jan 2002 03:00:00 GMT
Sashi Obilisett
|
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PLI1.0: Multiple instantiation |
andi_car.. |
1 |
458 |
Thu, 03 Jan 2002 03:00:00 GMT
Swapnajit Mittr
|
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module x(a,a), what does that mean |
Vardhan Var |
3 |
462 |
Tue, 01 Jan 2002 03:00:00 GMT
Chandresh Pate
|
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How to break a verilog for loop |
Chandresh Pate |
0 |
461 |
Tue, 01 Jan 2002 03:00:00 GMT
Chandresh Pate
|
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synthesizable code to Find position of the first occourance |
Bhavi Saklech |
3 |
460 |
Tue, 01 Jan 2002 03:00:00 GMT
Dan Hopp
|
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Clock divider? |
yap... |
2 |
428 |
Sat, 12 Jan 2002 03:00:00 GMT
David Rogo
|
|
Verilog FAQ |
rajes.. |
0 |
455 |
Fri, 04 Jan 2002 03:00:00 GMT
rajes..
|
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