logical regions vs page table granularity 
Author Message
 logical regions vs page table granularity

Hello,

I am trying to understand some of the finer details with
regards to memory management.  I just wanted to make sure
my assumptions were correct.

For an XScale processor:

If CE is using "course" second level, page table entries
with "small" page references (assumption one) and CE
commits/allocates memory in 64KB "regions" does this mean
that bits 15:0 of the virtual address are zeroed and only
bits 16:19 are used to index the second level page table?  
Thus, only having a maximum of 2^4 = 16 unique entries?

Or does CE actually use "large" page table references?

I guess I'm trying to understand the correlation between
the logical 64KB "regions" and the actual physical page
tables.

Thanks in advance for your patience with the "fresh fish"
J.

Chris Kavanagh

Symbol Technologies - Winnipeg, Canada



Sat, 28 May 2005 02:13:57 GMT  
 
 [ 1 post ] 

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