Bad synchronous description ?? 
Author Message
 Bad synchronous description ??

Please, what does this mean ?
Which Free programs do you use to Synthesize you VHDL code ?

ERROR:Xst:827 - C:/Diplom/VHDL/Test/Test_Module.vhd (Line 56). Signal
pld_msp cannot be synthesized, bad synchronous description.

Thanks




Sat, 17 Apr 2004 19:17:12 GMT  
 Bad synchronous description ??
Martin Fischer a crit :

Quote:

> Please, what does this mean ?
> Which Free programs do you use to Synthesize you VHDL code ?

> ERROR:Xst:827 - C:/Diplom/VHDL/Test/Test_Module.vhd (Line 56).
> Signal pld_msp cannot be synthesized, bad synchronous
> description.

Hi
Maybe you should post your code so that we could see what's wrong with it and
understand this error message.

--
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/



Sat, 17 Apr 2004 21:04:48 GMT  
 Bad synchronous description ??


Quote:
>Please, what does this mean ?
>pld_msp cannot be synthesized, bad synchronous description.

It means you have written some legal VHDL that does not map to
hardware in a reasonable way.  From the error message I would guess
that you have written a clocked process, and that you have
done something that does not conform to the standard synthesisable
process templates.  Typical examples might be:

- in the "reset" branch of your clocked logic, assigning
  something that is not a constant to signal pld_msp;
- making an assignment to pld_msp in one of the two
  branches (clocked and reset) but not the other;
- writing a clocked process that does not include a rising
  or falling edge test;
- attempting to wait for a clock edge in two separate places
  in a process.

Quote:
>ERROR:Xst:827 - C:/Diplom/VHDL/Test/Test_Module.vhd (Line 56). Signal

This ---------------^^^^^^  is a give-away, no?  I suggest that you
get a good book on VHDL for synthesis.  I don't know about the
availability of VHDL books in German, sorry.  My favourite is
  Rushton, A: VHDL for Logic Synthesis (Wiley).
Many people recommend
  Ashenden, P: Designer's Guide to VHDL
which is also excellent (DON'T get "Student's Guide to VHDL",
it's nothing like as good).

There is also some excellent stuff at
   http://www.e-technik.uni-dortmund.de/
(check out the comp.lang.vhdl FAQ for more resources).

Quote:
>Which Free programs do you use to Synthesize you VHDL code ?

The only free synthesis tools I'm aware of are those, like XST,
that are bundled with FPGA development kits of various kinds.

You can get limited-time evaluation versions of the professional
tools like Leonardo Spectrum (www.exemplar.com) and Synplify
(www.synplicity.com).
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
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Sat, 17 Apr 2004 21:15:15 GMT  
 Bad synchronous description ??
Thanks,

I hope my Synthesis licenses and books will come
soon.
I have a clocked process and the output should
change at the rising edge. Any Idea ?

  count : PROCESS (MSP_CLK, MSP_PLD)
  BEGIN
    IF MSP_PLD'EVENT AND MSP_PLD ='1' THEN
    Senden <='1';
  end if;

    for i IN 1 TO 4 Loop
      IF MSP_CLK'EVENT AND MSP_CLK ='1' AND Senden ='1' THEN

    --PLD_MSP <=S1_Buffer;    <===DOES NOT FUNCTION

        PLD_MSP <='1';
    end if;
  end Loop;
  END PROCESS count;



Sun, 18 Apr 2004 00:37:23 GMT  
 Bad synchronous description ??
Martin Fischer a crit :

Quote:

> Thanks,

> I hope my Synthesis licenses and books will come
> soon.
> I have a clocked process and the output should
> change at the rising edge. Any Idea ?

>   count : PROCESS (MSP_CLK, MSP_PLD)
>   BEGIN
>     IF MSP_PLD'EVENT AND MSP_PLD ='1' THEN
>     Senden <='1';
>   end if;

>     for i IN 1 TO 4 Loop
>       IF MSP_CLK'EVENT AND MSP_CLK ='1' AND Senden ='1' THEN

>     --PLD_MSP <=S1_Buffer;    <===DOES NOT FUNCTION

>         PLD_MSP <='1';
>     end if;
>   end Loop;
>   END PROCESS count;

First, you should write two different processes, each with its own clock
(MSP_CLK and MSP_PLD)
Second, I don't understand what you loop does. What do you want your code to do?

--
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/



Sun, 18 Apr 2004 01:09:16 GMT  
 Bad synchronous description ??


Quote:
>I have a clocked process and the output should
>change at the rising edge. Any Idea ?

>  count : PROCESS (MSP_CLK, MSP_PLD)
>  BEGIN
>    IF MSP_PLD'EVENT AND MSP_PLD ='1' THEN
>    Senden <='1';
>  end if;

>    for i IN 1 TO 4 Loop
>      IF MSP_CLK'EVENT AND MSP_CLK ='1' AND Senden ='1' THEN

>    --PLD_MSP <=S1_Buffer;    <===DOES NOT FUNCTION

>        PLD_MSP <='1';
>    end if;
>  end Loop;
>  END PROCESS count;

Sorry Martin, there is no chance of synthesising this code.

First, you have a process with two clocks.  No tool I know can
synthesise this.  You must split it into two separate processes,
each with only one clock.  So, let's try that - and, by the way,
let's get rid of the ugly (sig'EVENT AND sig='1') construct...

  control_Senden: PROCESS (MSP_PLD)
  BEGIN
    IF Rising_edge(MSP_PLD) THEN
      Senden <='1';
    end if;
  end process; -- control_Senden

OK, this process is now synthesisable.  I don't really understand
its purpose, because Senden starts in an unknown state and is
driven to 1 by the first clock edge, but that's your design problem
and not a VHDL problem :-)

OK, now for the counter process.  Much more difficult.
You have two big mistakes in the VHDL for synthesis:

(1) Embedding the clock test in a loop.  Unless you have a
    behavioural synthesis tool, you can't do this.  Don't do it.
    Your hardware will have a counter or a state machine;
    your VHDL must also have some counter or state machine structure.
(2) Combining some other logic with the clock-edge test.  I think
    Senden is acting as a clock enable.  If so, you must use the
    standard form of clock-enable template.

Here's the correct framework for your code:

 count: PROCESS (MSP_CLK)
 BEGIN
   if rising_edge(MSP_CLK) then  -- Clock edge test, SEPARATE
     if Senden='1' then          -- Clock enable logic
       -- do all your logic in here,
       -- including a counter for the divide-by-4
     end if;
   end if;
 end process; -- count

But, horror, this block generates MSP_PLD !!!! Why are you using
a derived clock for the Senden logic?

Before you consider writing this in VHDL you MUST work out how to
do it as purely synchronous logic, with just one clock for every
flip-flop.  You MUST also think carefully about power-up reset;
in your code there is no way to get the various flip-flops into
a sensible initial state.

Sometimes you have to solve a problem that really needs multiple
or derived clocks.  But please, please don't try that until your
skills with standard fully-synchronous VHDL are quite a lot more
secure!  Do **anything** you can to force the whole design
to be fully synchronous.

Synthesis is never a replacement for understanding the hardware.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Sun, 18 Apr 2004 00:59:56 GMT  
 Bad synchronous description ??
THANKS,

Shure I can make a state machine, but I thought VHDL is much more
comfortabel than Abel.

I just want to send 4 or 5 Bits over one single Output when a Clock
from the other mikrocontroller comes and writing is enabled.

First I tried a while loop, but I found it doesnt function and then I tried
the for loop. How can I synthesize this loops ?



Sun, 18 Apr 2004 17:17:15 GMT  
 Bad synchronous description ??
Hi,
What is xst and where can I get it?

On Tue, 30 Oct 2001 13:15:15 +0000, Jonathan Bromley

Quote:

>XST



Sat, 24 Apr 2004 11:59:14 GMT  
 Bad synchronous description ??
Hi,
   It is Xilinx Synthesis Tool (I guess) that comes with the Webpack
for free from http://www.xilinx.com/webpack/index.html You will need
to register there for free first.

Good luck,
Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)


Quote:
> Hi,
> What is xst and where can I get it?

> On Tue, 30 Oct 2001 13:15:15 +0000, Jonathan Bromley

> >XST



Sat, 24 Apr 2004 12:18:28 GMT  
 
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