Model Tech and Vital VHDL netlists 
Author Message
 Model Tech and Vital VHDL netlists

Does anyone have experience using the Model Tech
VHDL simulator ( or any other sim ) with outputs from popular FPGA tools
like Altera and Xilinx.

I am considering buying the Model Tech VHDL simulator
to do system level simulations including routed FPGAs and
functional bus level timing models of the processor and other
I/O devices being used in the design.

How does one tell the Model Tech VHDL simulator to use the
the vital and SDF files output from the Xilinx or Altera tools?

Thanks for any help.

Dan Fabrizio



Wed, 19 Apr 2000 03:00:00 GMT  
 Model Tech and Vital VHDL netlists

Quote:

> Does anyone have experience using the Model Tech
> VHDL simulator ( or any other sim ) with outputs from popular FPGA
> tools
> like Altera and Xilinx.

> I am considering buying the Model Tech VHDL simulator
> to do system level simulations including routed FPGAs and
> functional bus level timing models of the processor and other
> I/O devices being used in the design.

> How does one tell the Model Tech VHDL simulator to use the
> the vital and SDF files output from the Xilinx or Altera tools?

> Thanks for any help.

> Dan Fabrizio


We sell a less costly VHDL simulator which supports VITAL for XILINX
and other FPGA vendors. It's called PeakVHDL and it sells for 1300.00
plus
500.00 for the viatl support. You can download a free copy from our
website, and I can send you tech notes on using the VITAL primitives.

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com

Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/



Wed, 19 Apr 2000 03:00:00 GMT  
 Model Tech and Vital VHDL netlists



Quote:
> Does anyone have experience using the Model Tech
> VHDL simulator ( or any other sim ) with outputs from popular FPGA tools
> like Altera and Xilinx.

> I am considering buying the Model Tech VHDL simulator
> to do system level simulations including routed FPGAs and
> functional bus level timing models of the processor and other
> I/O devices being used in the design.

> How does one tell the Model Tech VHDL simulator to use the
> the vital and SDF files output from the Xilinx or Altera tools?

You have to compile the vital libraries (once) and then make that library
visible to the simulator.  When you simulate your design (VSIM), there is
a tabbed form for setting up SDF (file, min/max, etc).  Very
straightforward.
Quote:
> Thanks for any help.

> Dan Fabrizio




Sat, 22 Apr 2000 03:00:00 GMT  
 
 [ 3 post ] 

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