opencores doing first silicon 
Author Message
 opencores doing first silicon

Hello everybody,

I am happy to announce OpenCores will be doing its first silicon (TSMC
0.25u, 5LM) using its current open source cores. Current idea is to put
together three 32-bit RISC cores (OR1320 + 2x OR1601), SDRAM & master
PCI controller, 2x Ethernet MAC, 2x serial UART, RTC & WDT. Something
similar like Intel's IXP1200 network processors. First operating system
for the chip will probably be Linux (also eCos and RTEMS will be
ported).

Since all cores are more or less still under development we would like
to invite more people to help us. Help is especially needed on Ethernet
MAC and PCI master cores. Also all other teams welcome any additional
help. Preferred HDL to be used for _current_ chip is Verilog (unless you
can supply netlists for Artisan 0.25u TSMC).

If you would like more information about OpenCores's mission and current
project please visit us at http://www.*-*-*.com/
about silicon project are not yet published.

regards, Damjan
--

http://www.*-*-*.com/

Sent via Deja.com http://www.*-*-*.com/
Before you buy.



Sun, 26 Jan 2003 03:00:00 GMT  
 
 [ 1 post ] 

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