generics defined in terms of generics? 
Author Message
 generics defined in terms of generics?

Does anyone know if the VHDL '93 standard allows
generics to be defined in terms of other generics in
the same list?

For example,

generic (
...
        REG_WIDTH   : natural := 8;
        RESET_VALUE : std_logic_vector(0 to REG_WIDTH-1) := (others => '0');
...
)

is intended to be part of the parameterization (through generics) of
a register. We use the register's width to define the vector that
gives its reset value. (The presence of default values is not intended
to limit generality; the defaults may be overriden.)

I have found that Synplicity synplify pro 6.2 allows the above and
interprets it as expected. ModelSim SE 5.5a does not.
What does the VHDL language definition say?

(I don't see how we could define a reset value without
knowing how many bits it should contain.)

FO



Sun, 15 Feb 2004 05:34:07 GMT  
 generics defined in terms of generics?


Quote:
>Does anyone know if the VHDL '93 standard allows
>generics to be defined in terms of other generics in
>the same list?

>For example,

>generic (
>...
>        REG_WIDTH   : natural := 8;
>        RESET_VALUE : std_logic_vector(0 to REG_WIDTH-1) := (others => '0');
>...
>)

>is intended to be part of the parameterization (through generics) of
>a register. We use the register's width to define the vector that
>gives its reset value. (The presence of default values is not intended
>to limit generality; the defaults may be overriden.)

>I have found that Synplicity synplify pro 6.2 allows the above and
>interprets it as expected. ModelSim SE 5.5a does not.
>What does the VHDL language definition say?

... it says you can't do it.  Synplify shouldn't allow it.

Quote:
>(I don't see how we could define a reset value without
>knowing how many bits it should contain.)

I cope with this language feature in a number of ways.

0.  You could declare REG_WIDTH as a constant in a package.  This is
clean, but creates extra dependencies between files.

1.  If REG_WIDTH is less than 32, you could change the type of
RESET_VALUE to integer, e.g.

    reset_value : integer := 16#00000000#;

then later in the code have

    if reset = '1' then
        reg <= std_logic_vector(to_unsigned(reset_value, REG_WIDTH));

2.  Another way would be to declare reset_value as a std_logic_vector
of some arbitrarily wide width, say 32 bits.

    reset_value : std_logic_vector(31 downto 0) := (others => '0');

...

        reg <= reset_value(reg'range);

This sucks a bit though.

I'm sure there are several other ways of working around this language
feature.

I hope this helps,
Allan.



Sun, 15 Feb 2004 13:30:15 GMT  
 generics defined in terms of generics?

Quote:



> >Does anyone know if the VHDL '93 standard allows
> >generics to be defined in terms of other generics in
> >the same list?

> >For example,

> >generic (
> >...
> >        REG_WIDTH   : natural := 8;
> >        RESET_VALUE : std_logic_vector(0 to REG_WIDTH-1) := (others => '0');
> >...
> >)

> >is intended to be part of the parameterization (through generics) of
> >a register. We use the register's width to define the vector that
> >gives its reset value. (The presence of default values is not intended
> >to limit generality; the defaults may be overriden.)

> >I have found that Synplicity synplify pro 6.2 allows the above and
> >interprets it as expected. ModelSim SE 5.5a does not.
> >What does the VHDL language definition say?

> ... it says you can't do it.  Synplify shouldn't allow it.

> >(I don't see how we could define a reset value without
> >knowing how many bits it should contain.)

> I cope with this language feature in a number of ways.

> 0.  You could declare REG_WIDTH as a constant in a package.  This is
> clean, but creates extra dependencies between files.

> 1.  If REG_WIDTH is less than 32, you could change the type of
> RESET_VALUE to integer, e.g.

>     reset_value : integer := 16#00000000#;

> then later in the code have

>     if reset = '1' then
>         reg <= std_logic_vector(to_unsigned(reset_value, REG_WIDTH));

> 2.  Another way would be to declare reset_value as a std_logic_vector
> of some arbitrarily wide width, say 32 bits.

>     reset_value : std_logic_vector(31 downto 0) := (others => '0');

> ...

>         reg <= reset_value(reg'range);

> This sucks a bit though.

> I'm sure there are several other ways of working around this language
> feature.

3. Here is another idea. Just make RESET_VALUE an unconstrained
array:

      REG_WIDTH     : natural;
      RESET_VECTOR  : std_logic_vector;

It is not possible to have a default value any more, but this is
not a real limitation. Then, at instantiation, e.g.:

     REG_WIDTH    => 8,
     RESET_VECTOR => "00000001",

I think RESET_VECTOR would default to a "to" range, 0 to 7,
but not real sure. In worst case one might need to define a constant
to get the direction set correctly:

     constant  reg_reset_val : std_logic_vector(0 to 7) := "00000001";
     ...
     RESET_VECTOR => reg_reset_val,

IMHO the limitation on the scope of generics is a language definition mistake.
I don't think there is any compelling technical reason for
it and it prohibits many sensible generic definitions like the one
that started this thread. None of the "solutions" shown above are very satisfying.

VHDL has both home runs and whiffs and this is a whiff.
Some of the other wiffs are almost comical, like the absence
of a bracketed comment.

Quote:

> I hope this helps,
> Allan.

Bill


Tue, 17 Feb 2004 14:52:19 GMT  
 
 [ 3 post ] 

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