How to deal with Don't cares 
Author Message
 How to deal with Don't cares

How can I compare a Std-logic-vecor consisting of Dont'cares?

E.g.

SIGNAL A: std_logic_vector(7 downto 0)

   P1: PROCESS(A)
   BEGIN
       IF (A = "1-1100--") THEN
          B <= "11";
       ELSE
          B <= "00";
       END IF;
   END PROCESS;

The above code compiles, but doesn't simulate correctly? Why?
How can I overcome this problem without checking every bit of vector A ?

Thanks
Anil

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Thu, 19 Dec 2002 03:00:00 GMT  
 How to deal with Don't cares
Anil,

Take a look at the FAQ about don't cares at

http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#dont_cares

/ Jonas Thor

Quote:

>How can I compare a Std-logic-vecor consisting of Dont'cares?



Thu, 19 Dec 2002 03:00:00 GMT  
 
 [ 2 post ] 

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