FAQ1 general info 
Author Message
 FAQ1 general info




   _Preliminary Remarks_

   This is a monthly posting to comp.lang.vhdl containing general
   information. Please send additional information directly to the

   Last edited: june 1994 (Thanks for all corrections). Corrections and
   suggestions are appreciated.

   There are two other regular postings: part 2 lists books on VHDL, part
   3 lists products & services (PD+commercial).

Table of Contents

     * 0. General Information/Introduction
          + 0.1 The Group - why and what
          + 0.2 What is VHDL
          + 0.3 Before posting
     * 1. Abbreviations
     * 2. Official Contacts and Archives
     * 3. Frequently Asked Questions
          + 3.1 About Changes to the VHDL Standard
          + 3.2 Language Questions
               o 3.2.1 USE of library elements?
               o 3.3 PUBLIC DOMAIN Tools?
               o 3.4 VHDL Validation Suite available?
               o 3.5 Status of analog VHDL (AHDL, 1076.1)
               o 3.6 How can people get more information about AHDL
               o 3.7 Where to obtain the comp.lang.vhdl FAQ


0. General Information/Introduction

   The newsgroup comp.lang.vhdl was created in January 1991. It's an
       international forum to discuss ALL topics related to the language
       VHDL which is actually defined by the IEEE Standard 1076/87.
       Included are language problems, tools that only support subsets
       etc. NOT other languages such as Verilog HDL. This is not strict -
       if there is the need to discuss information exchange from EDIF to
       VHDL for example, this is a topic of the group. The group is
       unmoderated. Please think carefully before posting - it costs a
       lot of money! (Take a look into your LRM for example - if you
       still cannot find the answer, post your question, but make sure,
       that other readers will get the point). A chapter for frequently
       asked questions about the language will later be added to this
       regularly posted information - as they appear on the net. If
       necessary for the amount of information, this posting will
       possibly be split into separate postings for each chapter.

   VHDL-1076 (VHSIC (Very High Speed Integrated Circuits) Hardware
       Description Language) is an IEEE Standard since 1987. It is "a
       formal notation intended for use in all phases of the creation of
       electronic systems. ... it supports the development, verification,
       synthesis, and testing of hardware designs, the communication of
       hardware design data ..." [Preface to the IEEE Standard VHDL
       Language Reference Manual] and especially simulation of hardware
       descriptions. Additionally VHDL-models are a DoD requirement for

       Today simulation systems and other tools (synthesis, verification
       and others) based on VHDL are available. The VHDL users community
       is growing fast. Several international conferences organized by
       the VHDL Users Groups(s) have been held with relevant interest.
       Other international conferences address the topic with growing
       interest as well (Conference on Hardware Description Languages
       -CHDL-, [European] Design Automation Conference -[Euro]DAC ...).

     * - read the 3 FAQ's - they possibly answer your questions
     * - question about the language: try to find out in your LRM

1. Abbreviations

   AHDL:  Analog Hardware Description Language, s. VASAG

   BBS:   Bulletin Board System

   DoD:   USA Department of Defense

   FAQ:   Frequently Asked Questions

   IEEE:  The Institute of Electrical and Electronics Engineers. In case
          of VHDL, they defined the standard 1076

   LRM:   Language Reference Manual

          Tester Independent Support Software System

          VHDL Analog SubPAR Analysis and Standardization Group

   VASG:  VHDL Analysis and Standardization Group

   VFE:   VHDL Forum Europe

   VHDL:  VHSIC Hardware Description Language

          Very High Speed Integrated Circuits - A program of the DoD

   VI:    VHDL International

   VUG:   VHDL User's group. See below.

   VIUF:  VHDL International Users Forum

   VUG:   VHDL Users Group, see below

          Waveform Vector and Exchange Specification, proposed IEEE


2. Official Contacts and Archives

   VHDL User's group. VHDL International Users Forum
          The first (VUG) was transformed into the second (VIUF) in 1991.
          VIUF is Chaired by Allen M. Dewey and is a chapter and thus
          sponsored by VHDL International (VI).

          They organize conferences, send a newsletter (paper) and have
          some other activities. Point of contact is:

     Box 950 MS P360 Poughkeepsie, NY 12602 US +1 (914) 435-6040

   VHDL International

    VHDL International +1 415-329-0578 407 Chester Street 1 800-554-2550

    ford.edu (email)

          Current (Standards) Groups on the VHDL International Internet
          Services System (6 December, 1993, ver 1.4)

     * Name code-name
     * Die Industry Group ((bare) Die Info Exchange Format) die
     * IBIS Open Forum (I/O Buffer Info Spec) ibis
     * IEEE CS DASC VHDL EDIF Interoperability WG vhdledif
     * IEEE CS DASC VHDL Math Package WG math
     * IEEE CS DASC VHDL Parallel Simulation WG parallel
     * IEEE CS DASC VHDL Shared Variable WG svwg
     * IEEE CS DASC VHDL Synthesis WG vhdlsynth
     * VHDL International (VI) *vi
     * VI Local Chapter - Boston, MA boston_lc
     * VI Local Chapter - Phoenix, AZ phoenix_lc
     * VI Local Chapter - San Diego, CA sandiego_lc
     * VI Local Chapter - Silicon Valley (Local Users Group) svlug
     * VITAL (VHDL Initiative Towards ASIC Libraries) vital
     * * General email discussion group not available

   To find out more info about a group, send an email request to:

          To get added to their email discussion group and be made aware
          of activities, email your email address to:

          To submit a message to an email discussion group, email a

          Most of these groups have active file repositories also
          (including an archive of all email discussion traffic). Check
          either the "vi" or "pub" directories for the group of interest.

    ftp vhdl.org, login anonymous

          is ignored. If a line in the body begins with the word "help",
          then a descriptive file of commands available is sent. You
          should always include the command: path <your_email_address>

   VHDL-Forum for CAD in Europe (VFE)
          is the European users group active in VHDL related topics &
          standardization efforts. VFE is open to all interested
          participants. Contact:

    Andreas Hohl (Chair) SIEMENS, Dept. ZFE IS EA Ref Otto-Hahn-Ring 6 81
    739 Munich Germany Phone: +49-89-636-41895 Fax: +49-89-636-44950 Emai

   French (speaking) VHDL Users' Group
          Is actually a 'French-Speaking' due to the presence of Swiss
          people. (Belgium, Luxemburg and Val d'Aoste people are
          welcome). Organization is taken in charge by

          The first meeting was in Grenoble, November 30th, 1993. There
          were around 45 people. The meeting was quite good.

   German speaking VHDL User's Group

   maintains the mailing list and manages the group.

   Russian VHDL Interest Group

    Prof. Tartanikov Information Systems Research Institute 129090 Moscow


   VHDL User's Group of Belarus

    Dr. Anatoly Prihozhy Institute of Engineering {*filter*}netics Academy of
    Sciences of Belarus 6 Surganov Str. 220012 Minsk, Republic of Belarus

   UK VHDL User's Group

    Lucas Advanced Engineering Centre - Dog Kennel Lane Shirley - Solihul
    l, W. Midlands B90 4JJ - England phone: +44-21-627-4141, FAX: +44-21-

   VHDL Users Group of Spain

   There are more national/regional groups - adresses unknown to me

   VHDL Newsletter

   Editor of the US Newsletter:

   Europe Editor of the European Newsletter

    J. Mermet, J. Rouillard Phone: 3+91 05 44 44, FAX 33+91 05 43 43 Inst
    itut Mediterraneen de Technologie Technopole de Chateau-Gombert 13415
     Marseille cedex -FRANCE-

          Mail a request to be added to the group of registered news
          subscribers to


          One can access the files online by "ftp"ing to account



   VASAG the AHDL, 1076.1 Study group
          The 1076.1 study group is maintaining an email bulletin board
          for distribution of announcements and as a forum for technical
          discussions. There are two email addresses that can be used to
          access this facility. The addresses and their respective
          coordinators are as follows:

          In Europe:

          In US:

   VHDL-EDIF Interoperability Working Group
          is actively soliciting participants to join the working group.
          This working group, under the Design Automation Standards
          Subcommittee (DASC) of the IEEE, has the charter to "Recommend
          techniques for model interoperability between VHDL and EDIF".
          All are welcome to participate.

          One of the initial goals identified is to develop an IEEE
          standard practice for netlist exchange between VHDL and EDIF.
          getting added to the email discussion group: please send your

          up for the group's use. If you do not have access to email and
          if you are interested in actively participating in this group,
          please call the chair, J. Bhasker, at 215-770-3983 (United
          States, Eastern Standard Time).

   This posting/FAQ

    Thomas Dettmer, University of Dortmund, Dept. of Computer Science I D
    44221 Dortmund (Germany) Phone: +49-231 755 6464, FAX: +49-231 755 65


     * The FAQ is also available by ftp on vhdl.org
       vi/comp.lang.vhdl/FAQ.* see VHDL International for details on
       accessing the server. They also plan an archive of the groups
     * The ACM SIGDA (Special Interest Group Design Automation) offers
       through a gopher server a large amount of info, besides other
       stuff, the FAQ of this group and an archive dating back to 1992.
       Gopher Address: kona.ee.pitt.edu ( Contact Address:


3. frequently asked questions

   There's not much until today - but I included those questions I've
          often heard from beginners. If someone feels, that a point
          should be included, please let me know.


   According to IEEE rules every five years a standard has to be
          reproposed and accepted. This can include changes. Because VHDL
          is relativly young, the restandardisation in 1992 included
          changes, and it will in 1997.

          Changes in VHDL92 include: groups, private types, shared
          variables, inclusion of foreign models in a VHDL description,
          shift operators, support of pulse rejection by a modified delay
          model, more syntactic consistency. First adopted tools are
          expected in winter 1993/4 -correct me if I'm wrong.


   This chapter tries to answer some questions about language details
          which appear more or less regulary on the net.

    3.2.1 USE of library elements?

   Often users believe, they can use names of libraries /= work by simply
          inserting a use clause in the source. The analyzer responds
          with error messages.

          Insert a library clause before the use clause and all should
          work fine. (See your LRM for details).

    3.2.2 GENERATE usage and Configuration

   The generate statement is a concurrent statement that contains other
          concurrent statements. Two forms exist: for and if generate.
          Example which uses both:

First: if i=0 generate
  Q: adder port map (A(0), B(0), Cin, Sum(0), C(0));
end generate;
G: for i in 1 to 10 generate
    Q: adder port map (A(i), B(i), C(i-1), Sum(i), C(i));
end generate;

   The components are adressed (e.g. for specification):

First.Q, G(1).Q to G(10).Q

   Note: that form is used in an external configuration. If you need it
          inside you have to insert a block in the generate statement and
          place your configuration specification within that block.

          If you have a VHDL'93 compliant tool, it's easier.

    3.2.3 Aggregates containing a single element

   The question is often, whether

        a : INTEGER;
SIGNAL s: single;
  s <= 1; -- first illegal try to assign
  s <= (1); -- second try, also not legal in VHDL

   is valid VHDL? It isn't. "Aggregates containing a single element
          association must always be specified using named association in
          order to distinguish them from parenthesized expressions." says
          the LRM.

  s <= (a => 1);

   is valid.


   Actually as far as I know, there is only few PD software on VHDL. If
          YOU know about something, please let us know. See products
          posting for more detailed information.


   YES. free for universities and $2000 for companies and governmental
          agencies. see monthly posting on products. (This info maybe a
          bit out of date - as far as I know there is a new approach to
          build such a suite - or is it a continuation of the same?)


   Language Design has begun. The goal of the 1076.1 effort is to produce
          an approved standard LRM by the end of 1994. Well - seems this
          will not be hold. For my best knowledge actually 1996 is
          planned. comments?


   The 1076.1 study group is maintaining an email bulletin board for
          distribution of announcements and as a forum for technical
          discussions. see above (official contacts).

    ftp://vhdl.org in vi/comp.lang.vhdl



    Tom Dettmer

phone: +49-231 755 6464, FAX: +49-231 755 6555
T. Dettmer, Dortmund University, Computer Science I, 44221 Dortmund, Germany

Sat, 22 Feb 1997 17:33:43 GMT  
 [ 1 post ] 

 Relevant Pages 

1. general info (FAQ1)

2. Request: General info required by the uninitiated...

3. New Robot info and general news site

4. MISC processor general info request

5. '96 Rochester Forth Conf. - general info repost

6. General Info request

7. general request for info

8. control references/refnums: general info

9. Need info on Data General

10. new to verilog-looking for general info.

11. request for general ada info

12. Need general info about ADA


Powered by phpBB® Forum Software