ANNOUNCEMENT: POLIS 0.4 Embedded System Framework 
Author Message
 ANNOUNCEMENT: POLIS 0.4 Embedded System Framework

Apologies in advance if you receive multiple copies of this message.
---

Dear colleague,

It is our pleasure to announce the public availability of the POLIS-0.4
co-design environment for control-dominated embedded systems.
POLIS offers an integrated interactive environment for specification,
co-simulation, formal verification, and synthesis of embedded systems
implemented as a mix of hardware and software components.
Most of the information about POLIS, including pointers to source and
object code (for various CPUs and OSes) is available at our WEB site
http://www.*-*-*.com/ ~polis

The software is available under the usual copyright rules of the
University
of California (see also
http://www.*-*-*.com/ :80/copyright.html ).

If you are interested, but do not have WEB access, please contact us via

Best regards,
                                      The POLIS Team
(currently including Felice Balarin, Massimiliano Chiodo, Alberto
Ferrari, Paolo Giusto, Harry Hsieh, Attila Jurecska, Marcello Lajolo,
Luciano Lavagno, Claudio Passerone, Claudio Sansoe', Ellen Sentovich,
Marco Sgroi, Kei Suzuki, Bassam Tabbara, Reinhard von Hanxleden, and
Alberto Sangiovanni-Vincentelli)

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Release Notes: Version 0.4 November 10, 1999

The main changes are in the Ptolemy simulation interface, that now
supports
multiple processors. In particular:
- the UC and PTLUC macros in the Makefile no longer pre-load the clock
cycle
information for the selected processors. The information is loaded
dynamically at run time by Ptolemy (section 9.2).
- Each SW CFSM can be mapped to a different CPU, as selected by the
resourceName star parameter in Ptolemy (Section 6.1). RTOS and interface
CFSM synthesis does NOT understand that yet (multi-processor will be
supported in future releases). Section 6.1.5 (entitled "Upgrading
netlists
produced by POLIS 0.3") lists other differences with respect to previous
versions. Please, read it before using Ptolemy on old (pre-0.4) designs.
- Simulation time is now in seconds, and all the standard Ptolemy
testbench
stars can be used (section 6.1).
- Software estimates can be refined by using an Instruction Set
Simulator
(an example ISS for the SPARC processor is included with the release;
see
section 6.5).
- Power analysis (via simulation) can now be carried out (section 6.6).
- An instruction cache can now be simulated (section 6.7)
- Support for simulation and synthesis based on VHDL (behavi{*filter*}for
simulation, synthesizable for synthesis) is greatly enhanced (sections
6.3
and 6.4).
- A self-guiding tutorial on using formal verification techniques with
POLIS
is now included, in directory $POLIS/examples/formal_verification.
---------

To add/remove your name from the POLIS mailing list, please go to our
home
page: http://www.*-*-*.com/ ~polis

Thank You.

-Regards,

POLIS Team.

--
Bassam Tabbara
Ph.D. Candidate
211-150 Cory Hall
EECS Department, U.C. Berkeley
Berkeley, CA 94720
Phone/Fax: (510) 643-5187 / (510) 643-5052
URL: http://www.*-*-*.com/ ~tbassam



Sat, 18 May 2002 03:00:00 GMT  
 
 [ 1 post ] 

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