clocks and clock enables in Xilinx 
Author Message
 clocks and clock enables in Xilinx

Can anyone help me with this one,
Previously a few designs were done in Abel which you can use the
global clock buffer to clock all your flip flops and the
frequency of the clocking was controlled by the clock enable
dedicated pin  i.e.

mysig.clk = myclock
mysig.ce  = myenable

In VHDL in a clocked process the synthesis tool should connect
the clock in the sensitivity list to the flops. However if you
then clock enable in the clocking process i.e.

If (rising_edge clock AND clock enable)  will this in effect gate
the clock through the (a) CLB then connect it to the flop

Also what would happen if you made the statement

If (rising_edge clock) then
 If clock enable then
....

Will this be obvious to the synthesizer to use the global clock.
and separate out the enable

Sorry but one more

Do you have to state the clock enable in the sensitivity list

I'm just a bit concerned that the logic to create the clock
enable will be gated with the main clock, losing the global clock  
properties for which it was intended.

Could someone explain the definitive way of explicitly stating
the clock enable pin on the CLB flip flops
thanks in advance
kev brand
development engineer
marconi electronics systems
edinburgh
scotland  



Tue, 10 Jul 2001 03:00:00 GMT  
 clocks and clock enables in Xilinx
In VHDL the 'proper' way of putting in a clock enabled flip flop (i.e.
something like a 74xx377) is something of the form...

process (clock)
    if rising_edge(clock)    -- or falling edge if you prefer
        if (clock_enable = '1') then
            Q <= D;
        else                -- This part is actually optional since without
an else clause VHDL
            Q <= Q;    -- will infer a latch.  Personally, I prefer to have
an else for every 'if'.
        end if;
    end if;
end process;

Note that the clock enable is not in the sensitivity list since the FF
output (Q) does not change in response to a change in 'clock_enable' only to
a change in clock.  Whether your synthesis tool actually maps the
clock_enable signal to a CE input of a logic block is a function of the tool
itself.  It probably will but you will need to check.  In general, never
change the 'if rising_edge(clock)' statement to include logic such as 'If
(rising_edge clock AND clock enable)'.  Many synthesis tools will{*filter*}on
this.  If you find that you really want a gated clock for some reason,
generate the signal explicitly and then use that signal in your if statement
'if rising_edge(gated_clock)'.



Tue, 10 Jul 2001 03:00:00 GMT  
 clocks and clock enables in Xilinx

Quote:

>Can anyone help me with this one,
>Previously a few designs were done in Abel which you can use the
>global clock buffer to clock all your flip flops and the
>frequency of the clocking was controlled by the clock enable
>dedicated pin  i.e.

>mysig.clk = myclock
>mysig.ce  = myenable

>In VHDL in a clocked process the synthesis tool should connect
>the clock in the sensitivity list to the flops. However if you
>then clock enable in the clocking process i.e.

>If (rising_edge clock AND clock enable)  will this in effect gate
>the clock through the (a) CLB then connect it to the flop

No.  You'll probably get a complaint from your synthesis tool about
"enabling expression not permitted outside wait statements" (which is the
error FPGA Express gives).  Note that a simulator won't have any problems
with your statement (ModelSim doesn't).

Quote:
>Also what would happen if you made the statement

>If (rising_edge clock) then
> If clock enable then

That is the correct syntax.

Quote:
>Will this be obvious to the synthesizer to use the global clock.
>and separate out the enable

Yes, the global clock is used.  If the FPGA architecture has a flip-flop
with clock enable, it will use it.  A clock enable, remember, is really
implemented as a selector for a "recirculating" 2:1 mux. That mux output
feeds the flipflop's D input.  The flipflop's output feeds one input of the
mux; your desired "D" input feeds the other.  If the clock enable is
asserted, the mux's input from your "D" input is selected; otherwise the
flop's Q output is fed back into the flipflop's input (hence the name
"recirculating").

The timing analysis tool takes that mux into account when calculating
timing.

I think all of the major FPGAs have use CE'd flipflops for all the flops.

Quote:
>Sorry but one more

>Do you have to state the clock enable in the sensitivity list

No, in fact, you shouldn't.  The flipflop responds only to the clock (and
perhaps an async reset).

Quote:
>I'm just a bit concerned that the logic to create the clock
>enable will be gated with the main clock, losing the global clock
>properties for which it was intended.

Nope, see above.

Quote:
>Could someone explain the definitive way of explicitly stating
>the clock enable pin on the CLB flip flops

assume:     clk is the clock
            ce is the (active high) clock enable
            d is the input
            q is the output

    ceflipflop : process (clk)
    begin
        if clk'event and clk = '1' then
            if ce = '1' then
                q <= d;
            end if;
        end if;
    end process ceflipflop;

you can use

    if rising_edge(clk) then

if your synthesizer supports it, same difference.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Tue, 10 Jul 2001 03:00:00 GMT  
 clocks and clock enables in Xilinx

Quote:

> In VHDL the 'proper' way of putting in a clock enabled flip flop (i.e.
> something like a 74xx377) is something of the form...

> process (clock)
>     if rising_edge(clock)    -- or falling edge if you prefer
>         if (clock_enable = '1') then
>             Q <= D;
>         else                -- This part is actually optional since without
> an else clause VHDL
>             Q <= Q;    -- will infer a latch.  Personally, I prefer to have
> an else for every 'if'.
>         end if;
>     end if;
> end process;

> Note that the clock enable is not in the sensitivity list since the FF
> output (Q) does not change in response to a change in 'clock_enable' only to
> a change in clock.  Whether your synthesis tool actually maps the
> clock_enable signal to a CE input of a logic block is a function of the tool
> itself.  It probably will but you will need to check.  In general, never
> change the 'if rising_edge(clock)' statement to include logic such as 'If
> (rising_edge clock AND clock enable)'.  Many synthesis tools will{*filter*}on
> this.  If you find that you really want a gated clock for some reason,
> generate the signal explicitly and then use that signal in your if statement
> 'if rising_edge(gated_clock)'.

Any reasons why you couldn't put the "if clock_enable= '1' " first ?
cos' I think it's looks "better" :)  

--Lasse                
--___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_----
Lasse Langwadt Christensen, MSEE (to be in 1999)
Aalborg University, Department of communication tech.    
Applied Signal Processing and Implementation (ASPI)      



Tue, 10 Jul 2001 03:00:00 GMT  
 clocks and clock enables in Xilinx

Quote:

> Can anyone help me with this one,
> Previously a few designs were done in Abel which you can use the
> global clock buffer to clock all your flip flops and the
> frequency of the clocking was controlled by the clock enable
> dedicated pin  i.e.

> mysig.clk = myclock
> mysig.ce  = myenable

> In VHDL in a clocked process the synthesis tool should connect
> the clock in the sensitivity list to the flops. However if you
> then clock enable in the clocking process i.e.

> If (rising_edge clock AND clock enable)  will this in effect gate
> the clock through the (a) CLB then connect it to the flop

> Also what would happen if you made the statement

> If (rising_edge clock) then
>  If clock enable then
> ....

> Will this be obvious to the synthesizer to use the global clock.
> and separate out the enable

I find this to be a very interesting question in light of the
difficulties I have had using three different VHDL compilers. They have
ranged all the way from "I won't use the CE even if you try to make me!"
to "Hey, I'll use the CE if I feel like it and you can't stop me!".

See my postings under the subject "Re: State machine (right or wrong)
pls advice".

--

Rick Collins


remove the XY to email me.



Wed, 11 Jul 2001 03:00:00 GMT  
 clocks and clock enables in Xilinx

Quote:

>In VHDL the 'proper' way of putting in a clock enabled flip flop (i.e.
>something like a 74xx377) is something of the form...

>process (clock)
>    if rising_edge(clock)    -- or falling edge if you prefer
>        if (clock_enable = '1') then
>            Q <= D;
>        else -- This part is actually optional since without an else clause
VHDL
>            Q <= Q;    -- will infer a latch.  Personally, I prefer to have
>                        -- an else for every 'if'.
>        end if;
>    end if;
>end process;

No, it *won't* infer a latch without the else clause.  The
"rising_edge(clock)" (or clock'event and clock = '1' if you're a Synopsys
slave) tells the tools to use a flipflop.  The "if clockenable" tells the
tools that you want to use the flipflop's clock enable.  The else is fine
for completeness but not necessary.

--  andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Fri, 13 Jul 2001 03:00:00 GMT  
 clocks and clock enables in Xilinx

Quote:


>>In VHDL the 'proper' way of putting in a clock enabled flip flop (i.e.
>>something like a 74xx377) is something of the form...

>>process (clock)
>>    if rising_edge(clock)    -- or falling edge if you prefer
>>        if (clock_enable = '1') then
>>            Q <= D;
>>        else -- This part is actually optional since without an else clause
> VHDL
>>            Q <= Q;    -- will infer a latch.  Personally, I prefer to have
>>                        -- an else for every 'if'.
>>        end if;
>>    end if;
>>end process;
> No, it *won't* infer a latch without the else clause.  The
> "rising_edge(clock)" (or clock'event and clock = '1' if you're a Synopsys
> slave) tells the tools to use a flipflop.  The "if clockenable" tells the
> tools that you want to use the flipflop's clock enable.  The else is fine
> for completeness but not necessary.

Actually, the else is *not* fine.  It requires that Q be readable, for
one.  And note that the value read on Q is not necessarily what is
driven on Q, so the statement is not a noop....

Regards,

Paul

--

OrCAD                  | www.orcad.com   |  tempo che si ama."
P.O. Box 71767         | 919-479-1670[v] |  --Claude Adrien Helvetius
Durham, NC  27722-1767 | 919-479-1671[f] |



Sat, 14 Jul 2001 03:00:00 GMT  
 clocks and clock enables in Xilinx

Quote:


>> No, it *won't* infer a latch without the else clause.  The
>> "rising_edge(clock)" (or clock'event and clock = '1' if you're a Synopsys
>> slave) tells the tools to use a flipflop.  The "if clockenable" tells the
>> tools that you want to use the flipflop's clock enable.  The else is fine
>> for completeness but not necessary.

>Actually, the else is *not* fine.  It requires that Q be readable, for
>one.  And note that the value read on Q is not necessarily what is
>driven on Q, so the statement is not a noop....

You're right, of course.  I guess I'm guilty of using a "synthesis subset"
of the language that I know works for this specific instance.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Sat, 14 Jul 2001 03:00:00 GMT  
 
 [ 8 post ] 

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