initial summary of petri net/VHDL papers. 
Author Message
 initial summary of petri net/VHDL papers.

Hi
about a week ago i sent out a message asking for references on petri net
papers related to VHDL.
I recieved several emails asking me to summarise the replies i got,
well here it is, i have left the originators emails etc on them so i
cent take credit for finding the following, if you emailed me and your
message is not here, sorry, they will probably appear in an updates version
of this which i will do in a couple of weeks, if i get time.

Thanks for all the replies, if you know of any not here then please email me
with the details.
Ian.
------------------------------------------------------------------------------
Subject: Petri net/VHDL papers

Ian,

You can look at our papers at

ftp site: ftp.ida.liu.se  /pub/labs/cadlab/papers/EURO-DAC-92.ps.gz
                     and  /pub/labs/cadlab/papers/EURO-DAC-94.ps.gz

or WWW: ftp://ftp.ida.liu.se/pub/labs/cadlab/papers
      and the same two papers EURO-DAC-92.ps.gz, EURO-DAC-94.ps.gz

Regards,
/Kris Kuchcinski

===============================================================
 Dr. Krzysztof Kuchcinski
 Dept. of Computer and
   Information Science                  tel. +46 13 281883
 Linkoping University                   fax: +46 13 282666

===============================================================

One person to contact is Prof Phil Wilsey at the University of

libraries for petri nets are actually available by anonymous ftp from
thor.ece.uc.edu. If you like Mosaic pages, then I believe the names of the
papers on the subject are at

http://www.*-*-*.com/ ~paw/

Hope this helps

Venkat
----------------------------------
Venkatram Krishnaswamy
Center for Reliable and High Performance Computing
University of Illinois
----------------------------------------------------------------------
SEE i-Logix, they wrote an entire tool surrounding the concept of VHDL
system level design using the petri-net flow methodology.  Not exactly
petri-nets, more Markov Chain processes, but close enough for government
work!

Randy B.


Subject: RE: VHDL Semantics and Petri Nets
X-MX-Comment: QUOTED-PRINTABLE message automatically decoded

%0 Conference Proceedings
%A Mller, J
%A Kr?mer, H
%D 1993
%T Analysis of Multi-Process VHDL Specifications with a Petri Net Model
%B EuroDAC
%I IEEE Computer Society Press
%C Hamburg, Germany

%X This paper presents a model to analyze behavioural multi-process VHDL
specifications used for optimizing system-level synthesis. To determine the
access conflicts to the global data signals the system behaviour must be
analyzed. Therefore the synchronization scheme is modelled as a Petri net,
which can be minimized by transformations. A reduced case graph is regarded
as state transition graph of the system states. To calculate the
probabilites of the access conflicts the probability to observe the system
in a certain state must be determined, which may be done by the stationary
distribution of a Markov chain.

%0 Conference Proceedings
%A Olcoz, Serafn
%A Colom, Jos Manuel
%D 1993
%T Toward a Formal Semantics of IEEE Standard VHDL 1076
%B EuroVHDL
%I IEEE Computer Society Press
%C Hamburg, Germany
%P 526-531
%K VHDL Hardware_Description_Languages Formal_Methods
%X There exists a strong necessity for a formal interpretation of VHDL.
This paper address this aspect. The formal model used for this purpose are
Coloured Petri Nets because can cover all aspects of VHDL. We start from
the underlying executable model of VHDL based on communicating processes.
The formal model of a VHDL description results from the specification in
Petri Net terms of the user-defined processes, the kernel process (VHDL
simulator) and the communicating links between them. This approach can also
be applied to other HDLs with the same underlying paradigm.

%0 Conference Proceedings
%A Olcoz, S
%A Colom, J M
%D 1993
%T VHDL Through the Looking Glass
%B VHDL Forum for CAD in Europe
%C Innsbruck, Austria
%P 13-22

%0 Conference Proceedings
%A Olcoz, S
%A Colom, J M
%D 1993
%T Petri Net Based Analysis of VHDL Programs
%B EuroVHDL
%C Stockholm, Sweden

%0 Conference Proceedings
%A Olcoz, S
%A Colom, J M
%D 1993
%T A Petri Net Approach for the Analysis of VHDL Descriptions
%B CHARME 93
%C Arles, France
%P 15-26

%0 Conference Proceedings
%A Damm, Werner
%A Josko, Bernhard
%A Schl?r, R
%D 1993
%T A Net-Based Semantics for VHDL
%B EuroVHDL
%I IEEE Computer Society Press
%C Hamburg, Germany
%P 514-519
%K VHDL Formal_Methods Hardware_Description_Languages
%X The VHDL standard gives only an informal description of the semantics of
VHDL. But to apply formal verification techniques a precise semantics
definition is necessary. This paper defines a formal semantics for VHDL
based on interpreted Petri nets. The presented semantics is compositional
and provides a link to automatic verification methods for VHDL based
designs.

Simon Read
----------
Compass Design Automation       Tel: +1 410 992 5700 1 221
5457 Twin Knolls Road           Fax: +1 410 992 3536
Columbia, MD 21045, USA

--
Ian G. Clark BSc.(ENG) ... (Dr. Wizard), Electronic and Electrical Engineering
Kings College London. (These comments are my own, not from my organisation)



Mon, 07 Jul 1997 00:47:19 GMT  
 initial summary of petri net/VHDL papers.

Quote:
who writes:
>SEE i-Logix, they wrote an entire tool surrounding the concept of VHDL
>system level design using the petri-net flow methodology.  Not exactly
>petri-nets, more Markov Chain processes, but close enough for government
>work!

No, the i-Logix model, based on Harel's Statecharts, has almost nothing
to do with Petri nets.  It's more akin to the synchronous languages
like Esterel.  It's a variant of hierarchical state machines.  To see
the difference clearly, a Petri net *may* fire when a transition is
enabled, but in a statechart transitions *must* occur precisely when
they become enabled.

It's certainly useful but it ain't Petri nets.

--

Phone: +1 415 694 1729



Tue, 08 Jul 1997 08:36:09 GMT  
 initial summary of petri net/VHDL papers.

Quote:
|> who writes:

|>
|> >SEE i-Logix, they wrote an entire tool surrounding the concept of VHDL
|> >system level design using the petri-net flow methodology.  Not exactly
|> >petri-nets, more Markov Chain processes, but close enough for government
|> >work!
|>
|> No, the i-Logix model, based on Harel's Statecharts, has almost nothing
|> to do with Petri nets.  It's more akin to the synchronous languages
|> like Esterel.  It's a variant of hierarchical state machines.  To see
|> the difference clearly, a Petri net *may* fire when a transition is
                                        ^^^^
Isn't this the definition of a Stochastic PN?

|> enabled, but in a statechart transitions *must* occur precisely when
                                            ^^^^^^

                        This is Standard PN??

|> they become enabled.
|>
|> It's certainly useful but it ain't Petri nets.
|>
|>
|> --

|> Phone: +1 415 694 1729



Sun, 13 Jul 1997 02:36:55 GMT  
 
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