Quote:
>ERROR:HDLParsers:3312 - E:\xilinx_webpack\bin\teloef/telleroef.vhd Line 42.
>Undefined symbol 'teller'.
>ERROR:HDLParsers:162 - E:\xilinx_webpack\bin\teloef/telleroef.vhd Line 76.
>Read symbol PROCESS, expecting IF.
>ERROR:HDLParsers:162 - E:\xilinx_webpack\bin\teloef/telleroef.vhd Line 85.
>Read symbol behavioral, expecting IF.
>What does these errors mean??
Line 42: Object Teller is never declared.
Line 76: The process statement may not be correct. However, fix line 42
first.
I recommend tht you compile your code with a good compiler like ModelSim or
NcSim.
Most vendors give away the compiler (i.e., will compile and elaborate), but you
have to pay for the simulator.
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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