struct and behav in VHDL and Verilog 
Author Message
 struct and behav in VHDL and Verilog

I've been trying to learn HDL's lately, especially VHDL.
For my master's thesis I may be generating HDL code of a processor,
and then synthesizing it into a layout to get some vital statistics
such as chip area, etc.

My question is, realistically, what langauge (VHDL or Verilog) is
best for this project? From my limited experience with these languages,
it seems VHDL is at a disadvantage, becuase you can't mix
behavi{*filter*}("process") and structural code in a VHDL architecture,
while you can in a Verilog module.

For instance, I just wrote a behavi{*filter*}VHDL architecture.
The entity had an input bus and output bus. The output bus
was simply a concatenation of the input bus, and an internally generated
bus. I wanted to somehow say this once and never need to say it again
in my code.  But instead, since it was behavioral, every time an event
was generated on the input or internal bus, I had to update the output bus
accordingly. This shouldn't be necessary. Is there a better way?

Comments please.  Thanks!

Matt

--
*********************************************************
Matt Gavin                          BSEE U of Iowa '93

*********************************************************



Wed, 05 Mar 1997 01:13:16 GMT  
 struct and behav in VHDL and Verilog

: My question is, realistically, what langauge (VHDL or Verilog) is
: best for this project? From my limited experience with these languages,
: it seems VHDL is at a disadvantage, becuase you can't mix
: behavi{*filter*}("process") and structural code in a VHDL architecture,
: while you can in a Verilog module.

This is absolutely not true.

: For instance, I just wrote a behavi{*filter*}VHDL architecture.
: The entity had an input bus and output bus. The output bus
: was simply a concatenation of the input bus, and an internally generated
: bus. I wanted to somehow say this once and never need to say it again
: in my code.  But instead, since it was behavioral, every time an event
: was generated on the input or internal bus, I had to update the output bus
: accordingly. This shouldn't be necessary. Is there a better way?

You don't show your code, but I assume that it looks something like this:

entity Processor is
    port(Input:  in  Bus;
         Output: out Bus);
end Processor;

architecture Behavior of Processor is
    signal Internal: Bus;
begin
    -- generate Internal bus....

    process (Input, Internal)
    begin
         Output <= Input & Internal;
    end process;
end Behavior;

If indeed this approximates your code, then here's another way:

architecture Dataflow of Processor is
    signal Internal: Bus;
begin
    -- generate Internal bus....

    Output <= Input & Internal;
end Dataflow;

--Paul

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Fri, 07 Mar 1997 04:21:27 GMT  
 struct and behav in VHDL and Verilog

|> I've been trying to learn HDL's lately, especially VHDL.
|> For my master's thesis I may be generating HDL code of a processor,
|> and then synthesizing it into a layout to get some vital statistics
|> such as chip area, etc.
|>
|> My question is, realistically, what langauge (VHDL or Verilog) is
|> best for this project? From my limited experience with these languages,
|> it seems VHDL is at a disadvantage, becuase you can't mix
|> behavi{*filter*}("process") and structural code in a VHDL architecture,
|> while you can in a Verilog module.
|>
|> For instance, I just wrote a behavi{*filter*}VHDL architecture.
|> The entity had an input bus and output bus. The output bus
|> was simply a concatenation of the input bus, and an internally generated
|> bus. I wanted to somehow say this once and never need to say it again
|> in my code.  But instead, since it was behavioral, every time an event
|> was generated on the input or internal bus, I had to update the output bus
|> accordingly. This shouldn't be necessary. Is there a better way?

I fixed this by making a separate process for the bus mixing.
i.e.

architecture behav of my_entity is
begin
        process1(clk)
        begin
                --change internal bus in 2 or 3 different places
                --output bus needs to be updated each time
        end process1;

        process2(input bus, internal bus)
        begin
                output bus <= internal bus & input bus;
        end process2;
end behav;

I was unaware that more than one process could exist within an architecture.

Also, I have gotten several emails saying that you can instantiate
stuff in a behavi{*filter*}VHDL architecture.  Thanks to everyone!

Matt
--
*********************************************************
Matt Gavin                          BSEE U of Iowa '93

*********************************************************



Sat, 08 Mar 1997 03:36:30 GMT  
 
 [ 3 post ] 

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