clocked and asynchronous process on same register!? 
Author Message
 clocked and asynchronous process on same register!?

Hey everyone:

I'm trying to create a process for a register that has asynchronous
writes and synchronous increments.  The writes take precedence.  Here's
my code - does anyone have any suggestions from a synthesis standpoint?
This seems the most troublesome portion of the design when it comes to
glitches and setup/hold violations.

Thanks,
DJS

please_help_me: PROCESS(reset,is_writing,addr_match,
                                   address(3 DOWNTO 0),data_in,clk)
BEGIN
  IF(reset = '0') THEN
        count <= (OTHERS => '0');
  ELSIF(is_writing = '1' AND addr_match = '1' AND
                address(3 DOWNTO 0) = "0001") THEN
        count <= data_in;
  ELSIF(rising_edge(clk)) THEN
        IF(increment = '1') THEN
           count <= count + 1;
        ELSE NULL;
        END IF;
  ELSE
        count <= count;
  END IF;
END PROCESS please_help_me;

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Sat, 22 Mar 2003 03:00:00 GMT  
 clocked and asynchronous process on same register!?

I would re-time the asynchronous writes, (to make them synchronous), before
applying them to the register process.

This would make the thing synthesizable, and reduce the chance of
meta-stability.

 - Bren

Quote:

> Hey everyone:

> I'm trying to create a process for a register that has asynchronous
> writes and synchronous increments.  The writes take precedence.  Here's
> my code - does anyone have any suggestions from a synthesis standpoint?
> This seems the most troublesome portion of the design when it comes to
> glitches and setup/hold violations.

> Thanks,
> DJS

> please_help_me: PROCESS(reset,is_writing,addr_match,
>    address(3 DOWNTO 0),data_in,clk)
> BEGIN
>   IF(reset = '0') THEN
> count <= (OTHERS => '0');
>   ELSIF(is_writing = '1' AND addr_match = '1' AND
> address(3 DOWNTO 0) = "0001") THEN
> count <= data_in;
>   ELSIF(rising_edge(clk)) THEN
> IF(increment = '1') THEN
>    count <= count + 1;
> ELSE NULL;
> END IF;
>   ELSE
> count <= count;
>   END IF;
> END PROCESS please_help_me;

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Sat, 22 Mar 2003 03:00:00 GMT  
 clocked and asynchronous process on same register!?

Quote:

>Hey everyone:

>I'm trying to create a process for a register that has asynchronous
>writes and synchronous increments.  The writes take precedence.  Here's
>my code - does anyone have any suggestions from a synthesis standpoint?
>This seems the most troublesome portion of the design when it comes to
>glitches and setup/hold violations.

>Thanks,
>DJS

>please_help_me: PROCESS(reset,is_writing,addr_match,
>                               address(3 DOWNTO 0),data_in,clk)
>BEGIN
>  IF(reset = '0') THEN
>    count <= (OTHERS => '0');
>  ELSIF(is_writing = '1' AND addr_match = '1' AND
>            address(3 DOWNTO 0) = "0001") THEN
>    count <= data_in;
>  ELSIF(rising_edge(clk)) THEN
>    IF(increment = '1') THEN
>       count <= count + 1;
>    ELSE NULL;
>    END IF;
>  ELSE
>    count <= count;
>  END IF;
>END PROCESS please_help_me;

Have you actually synthesised this? With what synthesiser and target?
This came up on SIWG recently, and the code should be synthesisable,
but you need:

(1) a target F/F which has *both* an async reset and an async preset
(2) a synth clever enough to know that it can transform the
high-priority load into some combinatorial logic driving the async
reset and preset

You should get rid of the 'else null' and 'else count <= count' -
they're redundant, and the synth may complain about the second one.
You may also find that your static timing analyser can't cope with the
resulting circuit because of the async controls.

Apparently, Synplify may be able to cope with this code. I've been
meaning to check this but I haven't got around to it yet. However,
your best option would certainly be to start again and make the
hardware synchronous.

Evan



Sat, 22 Mar 2003 03:00:00 GMT  
 clocked and asynchronous process on same register!?

Quote:
> Have you actually synthesised this? With what synthesiser and target?
> This came up on SIWG recently, and the code should be synthesisable,
> but you need:

> (1) a target F/F which has *both* an async reset and an async preset
> (2) a synth clever enough to know that it can transform the
> high-priority load into some combinatorial logic driving the async
> reset and preset

> You should get rid of the 'else null' and 'else count <= count' -
> they're redundant, and the synth may complain about the second one.
> You may also find that your static timing analyser can't cope with the
> resulting circuit because of the async controls.

> Apparently, Synplify may be able to cope with this code. I've been
> meaning to check this but I haven't got around to it yet. However,
> your best option would certainly be to start again and make the
> hardware synchronous.

> Evan

Evan,

I've been playing with this code again and found that timing is made a
lot better by using the clear and preset on the FFs of the register.  The
process looks something like this:

write_to_regs: PROCESS(...)
BEGIN
  IF(reset = '0')
        <clear registers>
  ELSIF(pci_writing = '1') -- this goes thru logic to the FFs preset
    IF(register_match = '1') THEN
      CASE address(3 DOWNTO 0) IS
                WHEN "0000" => stuff <= lb_data;
                ...
         WHEN OTHERS =>
                stuff <= stuff;
                ...
        END IF;
  ELSIF(rising_edge(clk))
    IF(increment_count1 = '1') THEN
        count1 <= count1_inc; --separate regsiter stores count1+1, load it
    END IF;
    ...
  ELSE
    stuff <= stuff;
    ....
  END IF;

END PROCESS;

In the real code, all is very explicit -- except the major problem left
after Leonardo synthesis is that a write to one register somehow fills
ALL registers with the same value.  I can see how it might do this if it
uses the preset pins.  How can I be explicit enough to work around this?
Has anyone else used clocked and asynchronous processes on the same
registers?

Thanks,

Dan

Sent via Deja.com http://www.deja.com/
Before you buy.



Sun, 06 Apr 2003 03:00:00 GMT  
 
 [ 4 post ] 

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