Clock division in VHDL? 
Author Message
 Clock division in VHDL?

hello,

I am working on a project that need a clock division in VHDL using
Altera Maxplus2, the problem of Maxplus2 is it doesn't support floating
point operation. If I want to divide the 80MHz clock to 32 MHz, any
idea how to get it done without using real data type?

Any information is highly appreciated!

kent

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Sat, 28 Jun 2003 21:20:25 GMT  
 Clock division in VHDL?
Hi Kent,

Ray Andraka replid to a similar problem that I had a few weeks ago.  If
you dont need an EXACT 32MHz, use digital synthesis for those weird non
integer diviser values.  Design an n bit incrementer that is clocked on
the 80MHz clock, with an increment value of k for each clock cycle.  The
MSB is the output clock.  the output frequency will be 80MHz*k/(2^n).
The more logic you add, the closer you converge to 32MHz.

If you do need an exact 32MHz, expect a non 50% duty cycle. I think you
can use a state machine -- for every 5 cycles of the 80MHz clock, your
output will be high for the first two cycles, low for the third, high for
the fourth and low for the fifth.  The output waveform will look weird,
but overall you'll get 32M rising edges per second.

-DJS

Quote:
> I am working on a project that need a clock division in VHDL using
> Altera Maxplus2, the problem of Maxplus2 is it doesn't support floating
> point operation. If I want to divide the 80MHz clock to 32 MHz, any
> idea how to get it done without using real data type?

> Any information is highly appreciated!

> kent

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http://www.deja.com/


Sun, 29 Jun 2003 05:33:56 GMT  
 Clock division in VHDL?
Hi,

Quote:


> > I am working on a project that need a clock division in VHDL using
> > Altera Maxplus2, the problem of Maxplus2 is it doesn't support floating
> > point operation. If I want to divide the 80MHz clock to 32 MHz, any
> > idea how to get it done without using real data type?

> What you try to do is a division by 2.5 If you'd draw some waves,
> the answer should becomne clear. I you use two counters, one clocked
> on the falling edge and one clocked on the rising edge, it is
> possible to construct two one bit signals from those that can be
> OR'ed together to give the 32MHz clock. The counters can be
> from 0 to 4 and they give a high signal when they are 0 and 1.

> (R = rising edge, F = falling edge of 80 MHz clock)

>    R F R F R F R F R F R F R F
>     -------             ------
>    |       |           |              Pos clocked signal
> ---         -----------
>       -------             ----
>      |       |           |            Neg clocked signal
> -----         -----------

>     =========           ======
>    |         |         |             OR'ed result = 32MHz
> ===           =========

> The thing to worry about is to start both counters at the
> correct moment. The amount of logic is minimal in the
> negedge clock domain, so clock buffering might not be
> needed. Note that this 32MHz signal probably have significant
> jitter.

The jitter is 6.25 ns peak to peak, with a fundamental frequency of 16
MHz.

The whole thing can be done in 6 flip flops, or 7 flip flops if a 50%
duty cycle is needed on the output.

Email for the source code.  (Remove the ".hates.spam" part of my email
address first.)

Regards,
Allan.
--

Agilent Technologies          Voice:  +61 3 9210 5527
Advanced Networks Division    Fax:    +61 3 9210 5550
347 Burwood Highway  Forest Hill 3131 Australia



Sun, 29 Jun 2003 09:45:45 GMT  
 
 [ 3 post ] 

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