Inserting a vector slice into another vector 
Author Message
 Inserting a vector slice into another vector

Hi
Does anyone have a better technique in VHDL to insert a slice of a
vector into another vector where the position of insertion is dynamic,
that's a signal?
The code below has been taken from a module that synthesizes, but I'm
not happy with it due to the amount of logic generated.

  signal vector1:       std_logic_vector(127 downto 0);
  signal vector2:       std_logic_vector(127 downto 0);
  signal insert_point1: integer range 0 to 64;

  p_test: process(clk)

    variable insert_point2: integer range 0 to 127;

  begin

    if clk'event and clk = '1' then

      insert_point2:= insert_point1 + 63;

      Do some stuff here...

      -- Now insert a 64-bit slice
      for i in 127 downto 0 loop
        if (i <= insert_point2) and (i >=insert_point1) then

          vector1(i) <= vector2(i);

        end if;

      end loop;

    end if;
  end process p_test;

Thanks in advance for your help
Yves



Tue, 19 Jul 2005 22:32:46 GMT  
 Inserting a vector slice into another vector
Quote:
>Does anyone have a better technique in VHDL to insert a slice of a
>vector into another vector where the position of insertion is dynamic,
>that's a signal?
>The code below has been taken from a module that synthesizes, but I'm
>not happy with it due to the amount of logic generated.

>  signal vector1:       std_logic_vector(127 downto 0);
>  signal vector2:       std_logic_vector(127 downto 0);
>  signal insert_point1: integer range 0 to 64;
>  p_test: process(clk)
>    variable insert_point2: integer range 0 to 127;
>  begin
>    if clk'event and clk = '1' then
>      insert_point2:= insert_point1 + 63;
>      Do some stuff here...
>      -- Now insert a 64-bit slice
>      for i in 127 downto 0 loop
>        if (i <= insert_point2) and (i >=insert_point1) then
>          vector1(i) <= vector2(i);

BEN: This for loop implies a big demux for control.
Some possible other techniques:
1. Try this outside a loop
    sig64_slice := your_64_bit_slice;
    vector1 <= vector2; -- write the whole thing if update is needed
    vector1(insert_point2 downto insert_point1) <= sig64_slice;
2. Concatenation
   vector1<= vector2(some_left_range) & your64slice & vector2(some_right_range)

You have to try them out and see what you get.  
Those are ideas.
--------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------



Wed, 20 Jul 2005 04:34:44 GMT  
 Inserting a vector slice into another vector

Quote:

> >Does anyone have a better technique in VHDL to insert a slice of a
> >vector into another vector where the position of insertion is dynamic,
> >that's a signal?
> >The code below has been taken from a module that synthesizes, but I'm
> >not happy with it due to the amount of logic generated.

> >  signal vector1:       std_logic_vector(127 downto 0);
> >  signal vector2:       std_logic_vector(127 downto 0);
> >  signal insert_point1: integer range 0 to 64;
> >  p_test: process(clk)
> >    variable insert_point2: integer range 0 to 127;
> >  begin
> >    if clk'event and clk = '1' then
> >      insert_point2:= insert_point1 + 63;
> >      Do some stuff here...
> >      -- Now insert a 64-bit slice
> >      for i in 127 downto 0 loop
> >        if (i <= insert_point2) and (i >=insert_point1) then
> >          vector1(i) <= vector2(i);
> BEN: This for loop implies a big demux for control.
> Some possible other techniques:
> 1. Try this outside a loop
>     sig64_slice := your_64_bit_slice;
>     vector1 <= vector2; -- write the whole thing if update is needed
>     vector1(insert_point2 downto insert_point1) <= sig64_slice;
> 2. Concatenation
>    vector1<= vector2(some_left_range) & your64slice & vector2(some_right_range)

> You have to try them out and see what you get.  
> Those are ideas.
> --------------------------------------------------------------------------
> Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

> Author of following textbooks:
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example ",  2001 isbn  0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
> ------------------------------------------------------------------------------

Thanks Ben,
I've already tried those ideas, but the synthesis tool complains of
not supporting dynamic slicing.
Cheers
Yves


Wed, 20 Jul 2005 20:08:36 GMT  
 Inserting a vector slice into another vector
Yves,
try this one:

       for i in 64 downto 0 loop
         if (i = insert_point1) then
           vector1(63+i downto i) <= vector2(63+i downto i);
           exit
         end if;
       end loop;

Since i is a constant, it shoud be synthesizable (synthesis tools unrool
the for loop...)

-Eyck



Fri, 22 Jul 2005 17:57:44 GMT  
 
 [ 4 post ] 

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