VHDL templates? 
Author Message
 VHDL templates?

I want to build something like a register file that passes named data in and out through
signals of a record type (see the VHDL outline below).  How do I make multiple instances
of this register file in a single design where each instance has a different set of
registers?

Thanks,
Paul Butler


National Instruments
Austin, TX

----------------------------------------------------------

package mytypes is

type data_t is
  record
    data1,
    data2 : std_logic_vector(7 downto 0);
    data3 : std_logic_vector(3 downto 0);
  end record;

subtype add_t is std_logic_vector(1 downto 0);

end mytypes;

use work.mytypes.all;

entity reg_file is
  generic
    (
      constant depth : in integer := 4;
    )
  port
    (
     clk : in std_logic;
     add : in add_t;
     rd, wt : in std_logic;
     data_in : in data_t;
     data_out : out data_t
    );
end reg_file;

architecture rtl of reg_file is

  type data_array_t is array(depth-1 downto 0) of data_t;

  signal data_array : data_array_t;

begin

  -- decode the address and rd and wt signals to load
  -- or recall data in the array.

end rtl;



Sat, 26 Jan 2002 03:00:00 GMT  
 
 [ 1 post ] 

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