VHDL models of Phase-Locked Loops 
Author Message
 VHDL models of Phase-Locked Loops

Does anyone have VHDL (Behavioural) models of Phase-Locked Loops. I
know that VHDL PLL models were successfully tried out at IBM, but have
no idea who was responsible.

Simon Curry     Bell-Northern Research Ltd, Stop 49   Ph.: (613) 763-2981
VHDL Tools          P.O. Box 3511, Station C          Fax: (613) 763-7241
                  Ottawa, Ontario, Canada, K1Y 4H7  Flame: 1-800-DEV-NULL

Sun, 14 Nov 1993 05:59:59 GMT  
 [ 1 post ] 

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