Variable component and instance names 
Author Message
 Variable component and instance names

Hi VHDL'ers,

I am looking to be able to write an entity and then declare and
instantiate that entity in a toplevel wrapper file. However, based on a
variable/constant in a package file I would like to be able to
automatically rename the origninal compoment entity, the component
declaration in the wrapper and also the instance name of that component
in the wrapper.

In Verilog I would use a file with

'define MY_COMPONENT_NAME    a_component
'define MY_COMPONENT_INST    instance_of_component

and then in the module I would use the following to call the component

'MY_COMPONENT_NAME    'MY_COMPONENT_INST

the effect that both of the above get replaced with "a_component
instance_of_component"

Anybody have any clues or suggestions?

Thanks,
Stephan

  stephan.neuhold.vcf
< 1K Download


Sun, 11 Sep 2005 01:02:47 GMT  
 Variable component and instance names

Quote:

> Hi VHDL'ers,

> I am looking to be able to write an entity and then declare and
> instantiate that entity in a toplevel wrapper file. However, based on a
> variable/constant in a package file I would like to be able to
> automatically rename the origninal compoment entity, the component
> declaration in the wrapper and also the instance name of that component
> in the wrapper.

The standard VHDL way to do this is with configurations.

The closest thing to a define in VHDL is an if...generate:

    plug_in_my_comp: if my_config = A generate
       my_comp: entity work.my_ent;
    end generate plug_in_my_comp;

Here's a related idea on using vhdl type enumerations as identifiers:

     see google groups: vhdl test_in_t

    -- Mike Treseler



Sun, 11 Sep 2005 02:06:21 GMT  
 Variable component and instance names

Thanks Mike!!

--Stephan

Quote:


> > Hi VHDL'ers,

> > I am looking to be able to write an entity and then declare and
> > instantiate that entity in a toplevel wrapper file. However, based on a
> > variable/constant in a package file I would like to be able to
> > automatically rename the origninal compoment entity, the component
> > declaration in the wrapper and also the instance name of that component
> > in the wrapper.

> The standard VHDL way to do this is with configurations.

> The closest thing to a define in VHDL is an if...generate:

>     plug_in_my_comp: if my_config = A generate
>        my_comp: entity work.my_ent;
>     end generate plug_in_my_comp;

> Here's a related idea on using vhdl type enumerations as identifiers:

>      see google groups: vhdl test_in_t

>     -- Mike Treseler

  stephan.neuhold.vcf
< 1K Download


Mon, 12 Sep 2005 21:49:25 GMT  
 
 [ 3 post ] 

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