Any opinions of SystemC vs VHDL? 
Author Message
 Any opinions of SystemC vs VHDL?

For those unaquainted SystemC is move towards using C++ in the place of (or with) VHDL for design Simulation and eventually Synthesis.  For more info see:   http://www.*-*-*.com/

Appreciating that SystemC is new, and it will be a little time before it reaches the tool maturity that we see in VHDL compilers/synthesis, I wondered what people's opinion was of using the language C++ as opposed to VHDL?  What do you see as being the
advantages and (and I guess more likely from this group) the disadvantages?

Anyone got any links to web pages with such discussions?

Thanks.  JamesCC.
--

Post replies to this newsgroup rather than my email. Thank you.



Fri, 08 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?
Quote:

> For those unaquainted SystemC is move towards using C++ in the place of (or with) VHDL for design Simulation and eventually Synthesis.  For more info see:   http://www.systemc.org/

> Appreciating that SystemC is new, and it will be a little time before it reaches the tool maturity that we see in VHDL compilers/synthesis, I wondered what people's opinion was of using the language C++ as opposed to VHDL?  What do you see as being the
> advantages and (and I guess more likely from this group) the disadvantages?

For me there are two advantages:
- It's simply a C++ library. You can translate it with any
  c++ compiler (like g++) and you can link it to everything
  you can link ordinary C++ to. Like matlab, any socket/www
  stuff or scripting languages. There is no clumsy simulator API
  for integration.
- You can do real high level stuff, like BDD's, AI and all
  this, provided you can get C/C++/fortran/whatever code that
  you can compile into ordinary object code.
As to synthesis, that's another matter. I'd love to see
me getting a free malloc/free implementation and synthesize it.
Same goes for standard software stuff like recursive tree traversal.
And, of course, then the language independence goes into the
bin. OTOH, does anybody feel capable to add a VHDL backend
to gcc? That'd solve a real lot of problems.

Quote:
> Anyone got any links to web pages with such discussions?

Uh, www.systemc.org?

Greetings!
Volker
--
"Isn't it just my luck. Some stranger says to me, "I LOVE YOU"
and next thing I know, I've got this virus..."



Fri, 08 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?

Quote:

> Appreciating that SystemC is new, and it will be a little time before
> it reaches the tool maturity that we see in VHDL compilers/synthesis,
> I wondered what people's opinion was of using the language C++
> as opposed to VHDL?  What do you see as being the
> advantages and (and I guess more likely from this group)
> the disadvantages?

Assuming that it works, people already fluent in C++ will like it.
The much smaller number of people already fluent in VHDL
will see it as an unnecessary preprocessor.

       -Mike Treseler



Fri, 08 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?

Quote:


>> Appreciating that SystemC is new, and it will be a little time before
>> it reaches the tool maturity that we see in VHDL compilers/synthesis,
>> I wondered what people's opinion was of using the language C++
>> as opposed to VHDL?  What do you see as being the
>> advantages and (and I guess more likely from this group)
>> the disadvantages?

>Assuming that it works, people already fluent in C++ will like it.
>The much smaller number of people already fluent in VHDL
>will see it as an unnecessary preprocessor.

oh, so we're back to having software people design hardware?

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke



Fri, 08 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?

Quote:



> >> Appreciating that SystemC is new, and it will be a little time before
> >> it reaches the tool maturity that we see in VHDL compilers/synthesis,
> >> I wondered what people's opinion was of using the language C++
> >> as opposed to VHDL?  What do you see as being the
> >> advantages and (and I guess more likely from this group)
> >> the disadvantages?

> >Assuming that it works, people already fluent in C++ will like it.
> >The much smaller number of people already fluent in VHDL
> >will see it as an unnecessary preprocessor.

> oh, so we're back to having software people design hardware?

The day will likely come.  The difference is less and less all the time.


Sat, 09 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?

Quote:




> > >> Appreciating that SystemC is new, and it will be a little time before
> > >> it reaches the tool maturity that we see in VHDL compilers/synthesis,
> > >> I wondered what people's opinion was of using the language C++
> > >> as opposed to VHDL?  What do you see as being the
> > >> advantages and (and I guess more likely from this group)
> > >> the disadvantages?

> > >Assuming that it works, people already fluent in C++ will like it.
> > >The much smaller number of people already fluent in VHDL
> > >will see it as an unnecessary preprocessor.

> > oh, so we're back to having software people design hardware?

> The day will likely come.  The difference is less and less all the time.

So, this will forward all software quality problems into hardware.

Janos Ero



Sat, 09 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?

Quote:



> > >Assuming that it works, people already fluent in C++ will like it.
> > >The much smaller number of people already fluent in VHDL
> > >will see it as an unnecessary preprocessor.

> > oh, so we're back to having software people design hardware?

> The day will likely come.  The difference is less and less all the time.

I agree that it good to keep the distinction between s/w and h/w.  S/w
engineers that explore the full capabilities of the VHDL language, can
easily write programs that don't have a hope to be able to be synthesised.

You have to write code in a method that allows you to map each sub block
in your own mind to h/w, a state machine in VHDL being the classic example.
We then hope, of course, that the synthesis performs a similar mapping.
These skill are important for h/w engineers and not so important for
us softies.

The question is can we do this in C++ as well as we can in VHDL?

Hopefully the day will come when we can write C/C++ code to run in
the simulations of C++ h/w code.  As a softie who test and validates
the ICs we develop I'm very keen to see this.

Regards. JamesCC
(a s/w engineer, but with h/w engineer's degree! :p)
---



Sat, 09 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?

Quote:

> I agree that it good to keep the distinction between s/w and h/w.  S/w
> engineers that explore the full capabilities of the VHDL language, can
> easily write programs that don't have a hope to be able to be synthesised.

It's also possible to write synthesizable VHDL processes
using data structures, local variables,
functions and procedures.

Quote:
> You have to write code in a method that allows you to map each sub block
> in your own mind to h/w, a state machine in VHDL being the classic example.
> We then hope, of course, that the synthesis performs a similar mapping.
> These skill are important for h/w engineers and not so important for
> us softies.

> The question is can we do this in C++ as well as we can in VHDL?

Mapping a program composed of some C++ subset
to some equivalent VHDL process seems quite possible.

Wiring the processes together and out to the port
pins seems like a significant problem for C++.

      -Mike Treseler



Sat, 09 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?

Quote:



> > >Assuming that it works, people already fluent in C++ will like it.
> > oh, so we're back to having software people design hardware?
> The day will likely come.  The difference is less and less all the time.

Microsoft is still hiring x86 assembly language gurus to program DirectX...

I think it's true that for what _a large chunk_ of businesses are willing to
pay someone to design, the difference in "write it in C++ and run the
synthesis tool" is becoming less and less as time goes by.  However, there
will always be interesting, challenging jobs out there that simply don't
lend themselves well to the automated approach.

In my experience the more challenging a field is, the lower _percentage_ of
goobers you end up with in the field.  PC programmers are a dime a dozen
these days, but there are a lot of really poor programmers out there that
are still "good enough" to get a job.  In fact, some of them seem to work
for certain large EDA companies that shall remain nameless. :-)

---Joel Kolstad



Sat, 09 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?
Quote:


> > I agree that it good to keep the distinction between s/w and h/w.  S/w
> > engineers that explore the full capabilities of the VHDL language, can
> > easily write programs that don't have a hope to be able to be synthesised.

> It's also possible to write synthesizable VHDL processes
> using data structures, local variables,
> functions and procedures.

> > You have to write code in a method that allows you to map each sub block
> > in your own mind to h/w, a state machine in VHDL being the classic example.
> > We then hope, of course, that the synthesis performs a similar mapping.
> > These skill are important for h/w engineers and not so important for
> > us softies.

> > The question is can we do this in C++ as well as we can in VHDL?

Well, I just did a cycle accurate model of an FSM. Just for fun
I used GOTOs and labels. Worked just a charm. When I go back to
VHDL I'll sure miss goto...
So, IMHO FSM's can be modeled very nice in C++.

Greetings!
Volker
--
I believe that children are our future --- {*filter*}, brutish, and short.



Sun, 10 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?
On Mon, 22 May 2000 17:29:38 -0700, "Andy Peters"

Quote:

>oh, so we're back to having software people design hardware?

Nooooooooooooooooo!

Cheers
Stuart
For Email remove "NOSPAM" from the address



Sun, 10 Nov 2002 03:00:00 GMT  
 Any opinions of SystemC vs VHDL?
Quote:

> On Mon, 22 May 2000 17:29:38 -0700, "Andy Peters"

> >oh, so we're back to having software people design hardware?

> Nooooooooooooooooo!

Why not? Looking forward for the first - patch -  release where
you have to glue a little piece of silicon to your original chip. :-)

Greetings!
Volker
--
I believe that children are our future --- {*filter*}, brutish, and short.



Mon, 11 Nov 2002 03:00:00 GMT  
 
 [ 12 post ] 

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