ORCAD EXPRESS / Synplicity (feeling stuck) 
Author Message
 ORCAD EXPRESS / Synplicity (feeling stuck)

    Well after reading all the negative press in Deja News about Orcad I
feel I may be the only one on the planet trying to do FPGAs and CPLDs with
Express.  I have 9.2, which we bought 1 year ago, right before Cadence
bought Orcad.  Orcad shipped me Synplify form Synplicity to replace Express.
I had used their schematic capture sw and it was pretty good for the price.
    A year ago I didn't have a PLD design to work on and now I have 2 - one
simple GAL6002 from Lattice and the second will probably be a Xylinx Virtex
or maybe one of the older XC4000 chips.  I am new to VHDL but have used
ABEL.

    Well getting the simple GAL design to work has been a challenge. I
decided to check out Orcad's hierarchical design methods using a mixed VHDL
and schematic capture method.  I down loaded Lattice's ISP expert starter
kit to do the place and route of the GAL.
    Well I got bit on a number of issues right off the bat.  The PLD project
wizard for Orcad did not include the GALs so I had to use a SPLD (Simple
PLD ) implementation.  Well there is a library called spld.olb which
contained some simple macros for counters, buffers, etc. which Orcad pulled
nicely into the hierarchical block as schematic elements.  I had one
hierarchical block which contained simple combinational logic which I
implemented as a VHDL module.

    The compile passed ok and I had can do a functional simulation and
everything looked ok. Then I tried to take the edif file to the Lattice
tools and found it couldn't handle a hierarchical edif file. I tried a flat
edif file from orcad too, but the Lattice tool didn't like it, I can't
remember why.  Anyhow I exported a vhdl netlist out of orcad and used that
in the IspExpert tools.  The Lattice tools are almost as confusing as Orcad.
Anyhow it eventually compiled but I had to go into the OrCAD spld.vhd file
 which has vhdl code for the spld macros used in the schematics)  and cut
and past the components used in the spld macros into separate vhd files
which I then imported into my ISPExpert project.  Sounds desperate doesn't
it!!!

    Well the design compiled in IspExpert but again the functional
simulation runs but I used 2 cascaded  4 bit counters (tff1-8) which totally
do not work in the timing simulation.  NOT even Close.  It looks like the
2nd counter does not count and the first stops after maxing out instead of
rolling over?  Do I trust this result, no! From what I can tell the
structure of device seems right but there are a lot of nodes with weird
names which I haven't a clue what they are.  It is not easy to trace them
down.

    To get to the point - Is anyone out there using ORCAD Epress. If so we
should start our own email support group or something.  Does anyone know if
the Syplicity tools work better with vendor PAR sw?  If I am having this
much trouble with a simple gal what will happen in the fpga!!  I really like
the hierarchical method using some schematic some vhdl and keeping the
details down in the blocks.  That part of Orcad seemed to work ok. If I go
to Xilinx design sw does it have this capability and how much does this all
cost?



Sat, 24 May 2003 09:23:03 GMT  
 ORCAD EXPRESS / Synplicity (feeling stuck)


(snip usual OrCAD complaints)
Quote:
>     To get to the point - Is anyone out there using ORCAD Epress. If
so we
> should start our own email support group or something.

(snip)

There is an OrCAD forum hosted by OrCAD, including a section on Express:

http://knowledge.orcad.com/~exchange

We use OrCAD, and Express 9.1.  We only use Express if forced to by a
customer.  We use it with schematic entry only, not VHDL.  Even with
schematic entry only, there are errors in some of the macros.  I would
hope that the Synplicity software (which we have received but have not
yet installed) would allow decent VHDL entry.  I would hesitate to mix
this with OrCAD schematic entry.

OrCAD Cpature is great for PCB schematics, but it is a minefield for
PLD schematics.

We like to use Viewdraw and Viewsim for CPLD and FPGA entry and
simulation.  I am told that you can also mix in HDL modules (as EDIF
netlists), but I have not tried it.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.

Sent via Deja.com http://www.deja.com/
Before you buy.



Sat, 24 May 2003 03:00:00 GMT  
 ORCAD EXPRESS / Synplicity (feeling stuck)

Quote:



> (snip usual OrCAD complaints)
> >     To get to the point - Is anyone out there using ORCAD Epress. If
> so we
> > should start our own email support group or something.
> (snip)

> OrCAD Cpature is great for PCB schematics, but it is a minefield for
> PLD schematics.

I would second that vote. I had a *very* bad runin with Orcad a couple
of years ago with a version 7 of the Express tools. I learned a very
important lesson there. Now I *always* verify tools before I shell out a
penny for them. If they won't let me trial run them through a small
project, I don't bother with them.

Xilinx has *free* synthesis tools available on their web site. I have
used them a bit, but I have not gotten to the point of testing a chip
yet.

Good luck, if you stick with Orcad, I think you are going to need it.

--

Rick "rickman" Collins


Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
URL http://www.arius.com



Sun, 25 May 2003 14:48:08 GMT  
 
 [ 3 post ] 

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