
Mixed VHDL and Verilog with Xilinx ISE
Dave,
Synthesize the VHDL module without I/O pads being added.
Synthesize the Verilog portion of it a black box of the VHDL module
written in Verilog.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Quote:
> Hello,
> I am looking for an app note or something to explain how to do mixed
> vhdl and verilog design using Xilinx ISE software.
> For instance I have an processor in vhdl code and want to integrate
> that into my verilog design.
> Dave C.