Mixed VHDL and Verilog with Xilinx ISE 
Author Message
 Mixed VHDL and Verilog with Xilinx ISE

Hello,

I am looking for an app note or something to explain how to do mixed
vhdl and verilog design using Xilinx ISE software.

For instance I have an processor in vhdl code and want to integrate
that into my verilog design.

Dave C.



Tue, 13 Sep 2005 03:30:11 GMT  
 Mixed VHDL and Verilog with Xilinx ISE
Dave,

Synthesize the VHDL module without I/O pads being added.
Synthesize the Verilog portion of it a black box of the VHDL module
written in Verilog.

Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)

Quote:

> Hello,

> I am looking for an app note or something to explain how to do mixed
> vhdl and verilog design using Xilinx ISE software.

> For instance I have an processor in vhdl code and want to integrate
> that into my verilog design.

> Dave C.



Tue, 13 Sep 2005 12:08:48 GMT  
 Mixed VHDL and Verilog with Xilinx ISE
Oops, I forgot to mention that you need to tell NGDBUILD where the
netlist generated from the VHDL part of the design is located.

Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)



Tue, 13 Sep 2005 12:34:42 GMT  
 Mixed VHDL and Verilog with Xilinx ISE
Kevin,

Thanks that seems easy enough

Dave C.

Quote:
> Oops, I forgot to mention that you need to tell NGDBUILD where the
> netlist generated from the VHDL part of the design is located.

> Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> you will do so within the newsgroup.)



Tue, 13 Sep 2005 21:30:49 GMT  
 
 [ 4 post ] 

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