Transport Delay Vs Inertial Delay 
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 Transport Delay Vs Inertial Delay


  I have a simple question about signal assignments in VHDL.
I know that there are two types of models, the TRANSPORT delay model
and the INERTIAL delay model.  Although I understand the mechanism
behind what each model does, I'm somewhat unsure of the design situations
in which each model is ideally suited.

  Does someone out there in netland have some design samples which would
illustrate the appropriate usages of these two models?  Is there a simple
rule of thumb to follow for the models (i.e.,  Always design with inertial
delay except in the situation when ....)?

  Thanks in advance,



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Tue, 06 Feb 1996 06:44:05 GMT  
 [ 1 post ] 

 Relevant Pages 

1. Transport Delay and Inertial Delay

2. Transport vs. Inertial....ooops (DELAY item)

3. inertial vs. transport delay

4. Inertial and transport delay in Verilog

5. Inertial and transport delay in Verilog

6. Transport/Inertial DElay's

7. Avoiding inertial delay in delay lines

8. Unit Delay vs. Zero Delay

9. delay until vs. delay relative

10. This week's Coding tip: modeling combinational logic with inertial delays

11. The inertial delay model

12. Inertial Delay in Aldec 4.2?


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