Error: Clock skew plus hold time of destination register exceeds register-to-register delay 
Author Message
 Error: Clock skew plus hold time of destination register exceeds register-to-register delay

Hi!!

"  Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to
'|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold time
required for '|bsp_in:73|intdata_2_.Q'  is 1.4ns - circuit cannot operate
because Clock skew plus hold time of destination register exceeds
register-to-register delay "

I encounter this problem when i've finished compiling the project & doing
the timing analysis. Most of the time, my design did not give me this error
mesg but it happened ocassionally. I changed other part of the circuit but
did not make any changes on the bsp_in portion. What can I do to ensure this
won't happen again? How can i put any constraint and where i should put it?
Thanks.

I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on PC,
targetted at flex10k30e.
Pls advice

MK



Mon, 02 Dec 2002 03:00:00 GMT  
 Error: Clock skew plus hold time of destination register exceeds register-to-register delay

Quote:
MK Yap writes:
> Hi!!
> "  Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to
> '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold time
> required for '|bsp_in:73|intdata_2_.Q'  is 1.4ns - circuit cannot operate
> because Clock skew plus hold time of destination register exceeds
> register-to-register delay "
> I encounter this problem when i've finished compiling the project & doing
> the timing analysis. Most of the time, my design did not give me this error
> mesg but it happened ocassionally. I changed other part of the circuit but
> did not make any changes on the bsp_in portion. What can I do to ensure this
> won't happen again? How can i put any constraint and where i should put it?
> Thanks.
> I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on PC,
> targetted at flex10k30e.
> Pls advice

Use a different version of Maxplus2.  9.24 (older) and 9.6 (newer) seem
to be fine.

-- Jamie



Tue, 10 Dec 2002 03:00:00 GMT  
 Error: Clock skew plus hold time of destination register exceeds register-to-register delay
Hi!

It still happens in max+plus2 9.62. I was wondering if it is my design
problem or VHDL synthesizer or max+plus2 problem. Using quartus fitter
solved this problem.... wierd...

My question is: Is this error caused by the software(should maxplus2 take
care of this?) or design?? I did not put any constraint on my design.

MK


Quote:
> MK Yap writes:
> > Hi!!
> > "  Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to
> > '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold
time
> > required for '|bsp_in:73|intdata_2_.Q'  is 1.4ns - circuit cannot
operate
> > because Clock skew plus hold time of destination register exceeds
> > register-to-register delay "

> > I encounter this problem when i've finished compiling the project &
doing
> > the timing analysis. Most of the time, my design did not give me this
error
> > mesg but it happened ocassionally. I changed other part of the circuit
but
> > did not make any changes on the bsp_in portion. What can I do to ensure
this
> > won't happen again? How can i put any constraint and where i should put
it?
> > Thanks.

> > I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on
PC,
> > targetted at flex10k30e.
> > Pls advice

> Use a different version of Maxplus2.  9.24 (older) and 9.6 (newer) seem
> to be fine.

> -- Jamie



Tue, 10 Dec 2002 03:00:00 GMT  
 Error: Clock skew plus hold time of destination register exceeds register-to-register delay
Hi,

   While I belive all FPGA vendor will work properly when you connect
directly FF to FF inspite of this warning, when it come to asic we
simple add buffer between the two FF's.

So you might want to do this, as it will not effect the design and will
remove this msg. (of course you might need two buffers or on the other
hand use a smaller buffer, just choose a one that his time (min) delay
is a bit more than what the msg complain).

have a nice day

   Illan



Quote:
> Hi!!

> "  Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to
> '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold
time
> required for '|bsp_in:73|intdata_2_.Q'  is 1.4ns - circuit cannot
operate
> because Clock skew plus hold time of destination register exceeds
> register-to-register delay "

> I encounter this problem when i've finished compiling the project &
doing
> the timing analysis. Most of the time, my design did not give me this
error
> mesg but it happened ocassionally. I changed other part of the
circuit but
> did not make any changes on the bsp_in portion. What can I do to
ensure this
> won't happen again? How can i put any constraint and where i should
put it?
> Thanks.

> I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on
PC,
> targetted at flex10k30e.
> Pls advice

> MK

Sent via Deja.com http://www.deja.com/
Before you buy.


Tue, 10 Dec 2002 03:00:00 GMT  
 Error: Clock skew plus hold time of destination register exceeds register-to-register delay
This problem often arises when you gate the clock going to the destination
register (obviously, the gating adds delay).  For this reason, gated clocks are
generally to be avoided.  Adding a buffer between source and destination register,
as one of your respondents suggested, is not only inelegant but tricky, in that
place-and-route software generally removes such added logic as part of its
minimization algorithm.
Quote:

> MK Yap writes:
> > Hi!!
> > "  Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to
> > '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold time
> > required for '|bsp_in:73|intdata_2_.Q'  is 1.4ns - circuit cannot operate
> > because Clock skew plus hold time of destination register exceeds
> > register-to-register delay "

> > I encounter this problem when i've finished compiling the project & doing
> > the timing analysis. Most of the time, my design did not give me this error
> > mesg but it happened ocassionally. I changed other part of the circuit but
> > did not make any changes on the bsp_in portion. What can I do to ensure this
> > won't happen again? How can i put any constraint and where i should put it?
> > Thanks.

> > I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on PC,
> > targetted at flex10k30e.
> > Pls advice

> Use a different version of Maxplus2.  9.24 (older) and 9.6 (newer) seem
> to be fine.

> -- Jamie



Wed, 01 Jan 2003 03:00:00 GMT  
 Error: Clock skew plus hold time of destination register exceeds register-to-register delay



Quote:
> This problem often arises when you gate the clock going to the destination
> register (obviously, the gating adds delay).  For this reason, gated clocks are
> generally to be avoided.  Adding a buffer between source and destination register,
> as one of your respondents suggested, is not only inelegant but tricky, in that
> place-and-route software generally removes such added logic as part of its
> minimization algorithm.

"generally to be avoided" is putting it mildly, at least in the FPGA
context.  I would have said "state of sin" or "not supported".

That technique is left over from the old TTL/MSI days when many chips
didn't have clock-enable pins.

The only reason I can think of to actually put a gate on the clock
path today would be to save power when you are really desperate.

--
These are my opinions, not necessarily my employers.  I hate spam.



Thu, 02 Jan 2003 03:00:00 GMT  
 Error: Clock skew plus hold time of destination register exceeds register-to-register delay

Quote:



> > This problem often arises when you gate the clock going to the destination
> > register (obviously, the gating adds delay).  For this reason, gated clocks are
> > generally to be avoided.  

> "generally to be avoided" is putting it mildly, at least in the FPGA
> context.  I would have said "state of sin" or "not supported".

actually it's 'state of the art' for serious power savings, and the tools
are slowlt catching up - another reason for more closely integrated
synthesis and P&R tools ....

I think I read somewhere transmeta have something like 10k gated
clocks - and broke some timing tool they were using as a result
(take my numbers with a grain of salt - it's a dim recollection)

        Paul Campbell



Thu, 02 Jan 2003 03:00:00 GMT  
 
 [ 7 post ] 

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