Post P&R Verilog/VHDL netlist 
Author Message
 Post P&R Verilog/VHDL netlist

Can we generate Post P&R Verilog or VHDL netlist from ISE that can be
synthesiable ? I used ngd2ver but the output verilog netlist contains
lots of statements that are not synthesizable. Same is the case with
VHDL.

Thanks

-Vs



Mon, 21 Nov 2005 02:58:04 GMT  
 Post P&R Verilog/VHDL netlist
Have a look at the first lines of the generated VHDL (and probably also the
Verilog) code:
-- The output of ngd2vhdl is a simulation model. This file cannot be
synthesized,
-- or used in any other manner other than simulation. This netlist uses
simulation
-- primitives which may not represent the true implementation of the device,
however
-- the netlist is functionally correct. Do not modify this file.

You can perform a simulation with timing. The ISE tool also generated an
SDF file (contains the timing information).

Egbert Molenkamp



Quote:
> Can we generate Post P&R Verilog or VHDL netlist from ISE that can be
> synthesiable ? I used ngd2ver but the output verilog netlist contains
> lots of statements that are not synthesizable. Same is the case with
> VHDL.

> Thanks

> -Vs



Mon, 21 Nov 2005 03:41:06 GMT  
 Post P&R Verilog/VHDL netlist

Quote:

> Can we generate Post P&R Verilog or VHDL netlist from ISE that can be
> synthesiable ? I used ngd2ver but the output verilog netlist contains
> lots of statements that are not synthesizable. Same is the case with
> VHDL.

You're missing the point of the post P&R HDL file.  The design has
already been synthesized (and placed and routed).

You use this file (with the .sdf) to perform a post-layout timing
simulation on your design.

-a



Tue, 22 Nov 2005 09:00:06 GMT  
 Post P&R Verilog/VHDL netlist


Quote:
> Can we generate Post P&R Verilog or VHDL netlist from ISE that can be
> synthesiable ? I used ngd2ver but the output verilog netlist contains
> lots of statements that are not synthesizable. Same is the case with
> VHDL.

> Thanks

> -Vs

I've got no idea why anyone would like to do this. In software terms, this
sounds like taking assembler code resulting from compilation, insert it in
your source code again, and try to recompile/optimize it again like a kind
of recycling strategy? Perhaps you believe to have found an easy path to
convert a Xilinx design (of which you may not have the design HDL code) into
another FPGA technology through synthesis? This won't work however.
Again, I can't think of any good reason for what you're doing. Post-layout
(timing) simulation is the only goal of these files, in conjunction with SDF
timing info.

Regards,

Jaap



Tue, 29 Nov 2005 03:16:31 GMT  
 
 [ 4 post ] 

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