(after 3 ns )in VHDL==>(???) SystemC 
Author Message
 (after 3 ns )in VHDL==>(???) SystemC

Hi all,
I want to translate a vhdl code to systemc.I know that I can convert
"wait for n ns"
to "wait(n)" method in systemC, but what is the solution for:

as a concurrent statement:  
   a<= a1 after 4 ns, a2 after 10 ns;

I know that I can solve my problem using a temporary variable for a1,
a2,.. , but this solution envolves some complex calculations.
Is there any direct equivalant feature in timing models of systmc?

Also I will thank you if you evaluate my current solution.

-my current solution for concurrent signal assignment:
   process
       variable a1temp,a2temp;
       begin
          a1temp := a1;
          a2temp := a2;
          wait for 4 ns;
          a <= a1temp;
          wait for 6 ns;    --10-4 = 6 ns
          a <= a2temp;
          wait on  a1,a2;
       end process;

0in a sequential statement part:
  b<= b1 after 4 ns, b2 after 10 ns;
  c<= c1 after 3 ns;

my current solution:
   process
       variable b1temp,b2temp,c1temp;
       begin
          b1temp := b1;
          b2temp := b2;
          c2temp := c2;
          wait for 3 ns;
          c <= c1temp;
          wait for 1 ns;    --4-3 = 1 ns
          b <= b1temp;
          wait for 1 ns;    --10-4 = 6 ns
          b <= b2temp;
          wait on  c1,b1,b2;
       end process;

sincerely
z.Karimi



Tue, 14 Jun 2005 22:58:30 GMT  
 (after 3 ns )in VHDL==>(???) SystemC



Quote:
> Hi all,
> I want to translate a vhdl code to systemc.I know that I can convert
> "wait for n ns"
> to "wait(n)" method in systemC, but what is the solution for:

> as a concurrent statement:
>    a<= a1 after 4 ns, a2 after 10 ns;

Mmm, I could not find a straightforward solution for it in the documentation
(look for words like: delay, inertial)

Quote:

> I know that I can solve my problem using a temporary variable for a1,
> a2,.. , but this solution envolves some complex calculations.
> Is there any direct equivalant feature in timing models of systmc?

> Also I will thank you if you evaluate my current solution.

I don't think this is the correct behavior. Remember that you have
a concurrent statement that is sensitive to a1 and a2. In case a1 and
a2 are stable for 10 ns it looks OK. But if a1 is changed earlier
the behaviour is different.

Quote:

> -my current solution for concurrent signal assignment:
>    process
>        variable a1temp,a2temp;
>        begin
>           a1temp := a1;
>           a2temp := a2;
>           wait for 4 ns;
>           a <= a1temp;
>           wait for 6 ns;    --10-4 = 6 ns
>           a <= a2temp;
>           wait on  a1,a2;
>        end process;

Egbert Molenkamp


Wed, 15 Jun 2005 23:34:04 GMT  
 (after 3 ns )in VHDL==>(???) SystemC


Quote:
> Hi all,
> I want to translate a vhdl code to systemc.I know that I can
convert
> "wait for n ns"
> to "wait(n)" method in systemC, but what is the solution for:

> as a concurrent statement:
>    a<= a1 after 4 ns, a2 after 10 ns;

There's no direct equivalent of concurrent statements in
SystemC, you would have to create the equivalent process and model
that using an SC_THREAD.

Quote:
> I know that I can solve my problem using a temporary variable
for a1,
> a2,.. , but this solution envolves some complex calculations.
> Is there any direct equivalant feature in timing models of
systmc?

No. If you look on the OSCI web site discussion forums, there have
been
discussions about creating an event queue primitive channel - you
might
want to look at those discussions.

Quote:
> Also I will thank you if you evaluate my current solution.

> -my current solution for concurrent signal assignment:
>    process
>        variable a1temp,a2temp;
>        begin
>           a1temp := a1;
>           a2temp := a2;
>           wait for 4 ns;
>           a <= a1temp;
>           wait for 6 ns;    --10-4 = 6 ns
>           a <= a2temp;
>           wait on  a1,a2;
>        end process;

> 0in a sequential statement part:
>   b<= b1 after 4 ns, b2 after 10 ns;
>   c<= c1 after 3 ns;

> my current solution:
>    process
>        variable b1temp,b2temp,c1temp;
>        begin
>           b1temp := b1;
>           b2temp := b2;
>           c2temp := c2;
>           wait for 3 ns;
>           c <= c1temp;
>           wait for 1 ns;    --4-3 = 1 ns
>           b <= b1temp;
>           wait for 1 ns;    --10-4 = 6 ns
>           b <= b2temp;
>           wait on  c1,b1,b2;
>        end process;

> sincerely
> z.Karimi

Your solutions look OK to me.

regards

Alan

--
Alan Fitch
[HDL Consultant]

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Mon, 20 Jun 2005 17:44:28 GMT  
 
 [ 3 post ] 

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