to_stdlogicvector and ModelSim 
Author Message
 to_stdlogicvector and ModelSim

I am currently upgrading our simulation enviroment from QuickHDL to
ModelSIM 5.3e. Unfortunately the code many times simulated with QuickHDL
crashes with

###### gocm_addrdec_rtl.vhd(98):     IF maddroutp_i(31 DOWNTO 16) =
to_stdlogicvector(x"1024") THEN
ERROR: gocm_addrdec_rtl.vhd(98): Subprogram "to_stdlogicvector" is
ambiguous.
ERROR: gocm_addrdec_rtl.vhd(98): type error resolving function call:
to_stdlogicvector

in the compile step using ModelSIM 5.3e.

What's wrong with ModelSIM (or with my code ;-) )?

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  ...

  ocm_en : PROCESS (maddroutp_i,s_regks1,bq_ocmwen_i,cbytep_i)
    ...
  BEGIN
    IF maddroutp_i(31 DOWNTO 16) = to_stdlogicvector(x"1024") THEN
      IF maddroutp_i(15 DOWNTO 14) /= "11" AND s_regks1 = '1' THEN
        bocmselp_o <= '1';  -- ocm selected when in kseg1 and base addr
ok
      END IF;
    ....

Thanks for your help!

Johann Notbauer

--
-------------------------------------------------------------------
Johann NOTBAUER                              COT Systemverification
Siemens AG Austria, PSE EZE TNA5
Erdberger Laende 26, A-1031 Vienna, Austria
Phone: +43 (1) 1707 36087, FAX: +43 (1) 1707 55670



Fri, 25 Jan 2002 03:00:00 GMT  
 to_stdlogicvector and ModelSim
Use of the -87 switch of vcom solves the problem.

Are there changes of VHDL93 in the behaviour with resolved type?

Johann Notbauer

Quote:

> I am currently upgrading our simulation enviroment from QuickHDL to
> ModelSIM 5.3e. Unfortunately the code many times simulated with QuickHDL
> crashes with

> ###### gocm_addrdec_rtl.vhd(98):     IF maddroutp_i(31 DOWNTO 16) =
> to_stdlogicvector(x"1024") THEN
> ERROR: gocm_addrdec_rtl.vhd(98): Subprogram "to_stdlogicvector" is
> ambiguous.
> ERROR: gocm_addrdec_rtl.vhd(98): type error resolving function call:
> to_stdlogicvector

> in the compile step using ModelSIM 5.3e.

> What's wrong with ModelSIM (or with my code ;-) )?

>   LIBRARY ieee;
>   USE ieee.std_logic_1164.ALL;
>   ...

>   ocm_en : PROCESS (maddroutp_i,s_regks1,bq_ocmwen_i,cbytep_i)
>     ...
>   BEGIN
>     IF maddroutp_i(31 DOWNTO 16) = to_stdlogicvector(x"1024") THEN
>       IF maddroutp_i(15 DOWNTO 14) /= "11" AND s_regks1 = '1' THEN
>         bocmselp_o <= '1';  -- ocm selected when in kseg1 and base addr
> ok
>       END IF;
>     ....

> Thanks for your help!

> Johann Notbauer

--
-------------------------------------------------------------------
Johann NOTBAUER
COT Systemverification
Siemens AG Austria, PSE EZE TNA5
Erdberger Laende 26, A-1031 Vienna, Austria
Phone: +43 (1) 1707 36087, FAX: +43 (1) 1707 55670



Fri, 25 Jan 2002 03:00:00 GMT  
 to_stdlogicvector and ModelSim
Hi,

Quote:

> I am currently upgrading our simulation enviroment from QuickHDL to
> ModelSIM 5.3e. Unfortunately the code many times simulated with QuickHDL
> crashes with

> ###### gocm_addrdec_rtl.vhd(98):     IF maddroutp_i(31 DOWNTO 16) =
> to_stdlogicvector(x"1024") THEN
> ERROR: gocm_addrdec_rtl.vhd(98): Subprogram "to_stdlogicvector" is
> ambiguous.
> ERROR: gocm_addrdec_rtl.vhd(98): type error resolving function call:
> to_stdlogicvector

> in the compile step using ModelSIM 5.3e.

The problem is caused by the function(s) to_stdlogicvector which exist
in two versions:

        function To_StdLogicVector (P: Bit_Vector)
                return std_logic_vector;

        function To_StdLogicVector (P: std_ulogic_vector)
                return std_logic_vector;

In VHDL'87, bit strings (such as x"1024") can only be of type
Bit_Vector. However, in '93, bit strings can be of any one-dimensional
array type that includes the values '1' and '0' (e.g. std_ulogic_vector).
Hence, the compiler does not know which function to call.

Use

         To_StdLogicVector(Bit_Vector'(x"1024"))

instead.

(Extracted from the FAQ (http://www.vhdl.org/comp.lang.vhdl/))

--
Edwin



Fri, 25 Jan 2002 03:00:00 GMT  
 to_stdlogicvector and ModelSim
Hi,
if the HDL-simulator understands Vhdl'93 you can omit the conversion-function
"to_std_logic_vector(...)".

J?rg



Sun, 03 Feb 2002 03:00:00 GMT  
 
 [ 4 post ] 

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