Different software 
Author Message
 Different software

Hi, my post is about the different software I see for HDL development.
I taught (cause I bought Xilinx Student Foundation F1.5) that, like C
compiler, you can only use the 'software package' (i.e,vhdl
compiler,the synthesizer,simulation) to do your design.

If I ask this question, it's because I went to vhdl.org web site, and
in a link, they talk about a company, Pixelwork, how design a LCD
controller.The team coded register transfer level (RTL) blocks in VHDL
and simulated them using Model Technology's Model Sim PE on Windows NT.
They worked to full system simulation using test benches on Windows NT
with Model Sim PE. In parallel, the team synthesized the design in the
UNIX environment using Synopsys' Design Compiler. From there, they
checked timing and made changes accordingly.

Does this mean that software are compatible between them with
a 'standard kind' of files?

Sent via Deja.com http://www.*-*-*.com/
Before you buy.



Tue, 28 Jan 2003 03:00:00 GMT  
 Different software
Hi,
  It is basically the way your RTL is written - if it follows the general
synthesis/compatibility guidelines, then you should not have any problem in
using different tools. It is the VHDL description that's portable.

Hope this clears up a bit (I am sure not fully though :-) )

Srini

Quote:
> Hi, my post is about the different software I see for HDL development.
> I taught (cause I bought Xilinx Student Foundation F1.5) that, like C
> compiler, you can only use the 'software package' (i.e,vhdl
> compiler,the synthesizer,simulation) to do your design.

> If I ask this question, it's because I went to vhdl.org web site, and
> in a link, they talk about a company, Pixelwork, how design a LCD
> controller.The team coded register transfer level (RTL) blocks in VHDL
> and simulated them using Model Technology's Model Sim PE on Windows NT.
> They worked to full system simulation using test benches on Windows NT
> with Model Sim PE. In parallel, the team synthesized the design in the
> UNIX environment using Synopsys' Design Compiler. From there, they
> checked timing and made changes accordingly.

> Does this mean that software are compatible between them with
> a 'standard kind' of files?

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Tue, 28 Jan 2003 03:00:00 GMT  
 Different software
Hi,

As Srini pointed out, VHDL is very portable.

What's not portable is the Foundation design environment.

The "project" files, and the simulations scripts are very
unique to that tool.

It is very advantageous to write your simulation "scripts"
in VHDL (or Verilog) rather than some propriatary language.

And some buzz words for you:

RTL:         In this case, they mean synthesisable code.
Test Bench:  The test scripts, written in VHDL.
RTL + Test Bench = Simulation Environment
RTL + Synopsis   = The chip netlist

Quote:
>> Does this mean that software are compatible between them with

a 'standard kind' of files?

Yup.  In this case the RTL and Bench were in 'standard kind'
VHDL.

Clear as mud?

Gary.

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Tue, 28 Jan 2003 03:00:00 GMT  
 
 [ 3 post ] 

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