IVC/VIUF Call For Papers 
Author Message
 IVC/VIUF Call For Papers

1998 INTERNATIONAL VERILOG HDL CONFERENCE AND VHDL INTERNATIONAL USERS'
FORUM
March 16 - 18, 1998 ? Santa Clara Convention Center ? Santa Clara, CA

IVC CALL FOR PAPERS
IVC provides a wonderful opportunity to exchange information in a
technical conference focused on HDL-based design for the electronics
industry.  Now is your opportunity to participate by submitting a paper
on one of topics listed below, or on some unique topic of your own.
Here is your chance to be recognized by a prestigious group of designers
and colleagues.

VIUF CALL FOR PAPERS
VHDL plays a key role in the design of state-of-the-art military,
commercial and academic electronic systems. The VIUF addresses research
and development results along with practical experience to support the
design and test of electronics systems. After ten years of success, the
VIUF continues to provide an excellent forum for researchers, users, and
vendors to discuss best practices in design and trends of the future.
With the VIUF once again co-located with the International Verilog HDL
Conference, this will be the premiere event to support the design
community with HDL-based methods.

IMPORTANT DATES:
Full Papers and Extended Tutorial Abstracts Due:  OCTOBER 31, 1997
Notification of Acceptance:  DECEMBER 8, 1997
Final Manuscripts Due:  JANUARY 12, 1998
Conference Dates:  MARCH 16 - 18, 1998

Ten copies of full manuscripts of papers or proposals for panels,
workshops, tutorials and presentations should be submitted before
OCTOBER 31, 1997 to the following address:

ATTN:
VIUF'98
Greg Peterson
Program Chair, Spring '98 VIUF
5305 Spine Rd., Ste. A
Boulder, CO  80301  USA
tel:   (303) 530-4562

IVC'98
Elliot Mednick
Program Chair, Int'l Verilog HDL Conference
5305 Spine Rd., Ste. A
Boulder, CO  80301  USA
tel:   (303) 530-4562

The paper should be between 1500 and 3000 words, double spaced with 1"
borders.  It may contain as many diagrams as needed to illustrate your
key points, but please limit the paper to a maximum of 8 pages.
Participants will be notified of acceptance by DECEMBER 8, 1997.  All
accepted paper presenters are awarded a  FULL CONFERENCE REGISTRATION.
All tutorial presenters are paid based on the number of attendees.

IVC SUBMISSION TOPICS
BEST PAPER AWARD
The IVC has instituted the following awards:
Best Paper Award   $750.00
Second Paper Award   $500.00
Third Paper Award   $250.00

Suggested topics are:
SYSTEM-LEVEL DESIGN
S1.  HW/SW Co-Design
S2.  Behavi{*filter*}Coding and Synthesis
S3.  Verilog and C Working Together
S4.  Verilog and Verilog-A Mixed-Signal Simulation
S5.  Cycle-Based Coding Techniques
S6.  Formal Verification
S7.  Board-Level

ASIC DESIGN
A1.  Design Re-use
A2.  Deep Sub-Micron Design Issues
A3.  Constraint-Driven Synthesis
A4.  Floorplan-Driven Logic Synthesis
A5.  Simulating Extremely Large ASICs
A6.  ASIC Prototyping
A7.  Emulation

FPGA DESIGN
F1.  Mixed-Level Design (Schematic + RTL)
F2.  Architecture Specific Optimization Techniques
F3.  Multiple-FPGA Partitioning and Testing
F4.  FPGA to ASIC Conversion
F5.  Verification of Retargeted Devices
F6.  State-Machine Design
F7.  Timing Issues
Also: Tutorial proposals, suggestions for panels, any other ideas.

VIUF SUBMISSION TOPICS
BEST PAPER AWARD
The VIUF has instituted the following awards:
Best Paper Award   $1076.00
Superior Paper Awards  $250.00

Suggested topics include:
V1. System Level Design Methods
V2. Hardware/Software Codesign
V3. Logic and State Machine Synthesis
V4. Behavi{*filter*}Synthesis
V5. VHDL/Verilog Cosimulation
V6. VHDL-AMS
V7. Formal Verification
V8. Constraint Support
V9. FPGA Design
V10. Reconfigurable Computing
V11. Performance Modeling
V12. Intellectual Property Capture, Protection, & Distribution
V13. Design Reuse
V14. Design for Test
V15. Testbench Support
V16. Virtual Prototyping
V17. Advanced VHDL Applications
V18. Simulation Techniques
V19. Emulation
Also: Tutorial proposals, suggestions for panels, any other ideas.

For information concerning the conference contact:
Lee Wood
c/o MP Associates, Inc.
5305 Spine Rd., Ste. A, Boulder, CO 80301
tel: (303) 530-4562 ? fax: (303) 530-4334

FOR THE LATEST INFORMATION SEE: www.hdlcon.org

VIUF Sponsored By:  VHDL INTERNATIONAL

--
Elliot Mednick                                      7 Tudor Drive, Suite
300
Wellspring Solutions, Inc.                          Salem, NH. 03079
                                                    (603) 898-1100



Sun, 02 Apr 2000 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. IVC/VIUF Call For Papers

2. Call for Papers: Joint IVC/VIUF

3. IVC call for papers

4. IVC '97 Call for papers

5. 1996 IVC Call for Papers

6. 1996 IVC Conference CALL FOR PAPERS

7. 1995 IVC call for Papers

8. 1995 IVC call for Papers

9. Final reminder: VIUF Fall 98 call for Workshops, Tutorials and Papers

10. Fall VIUF Workshop Call For Papers

11. VIUF CALL FOR PAPERS AND TUTORIALS

12. Fall VIUF Conference Call For Papers

 

 
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