FPGA specs 
Author Message
 FPGA specs

hi all
What is the difference between he Typical gates and Maximum System gates
specifications
For Altera EPXA1 these ratings are 100K and 263K respectively  what may be
the available gates for programming
regards
geeko


Sun, 04 Sep 2005 15:14:56 GMT  
 FPGA specs

Quote:
> hi all
> What is the difference between he Typical gates and Maximum System
gates
> specifications
> For Altera EPXA1 these ratings are 100K and 263K respectively  what
may be
> the available gates for programming

Try sci.electronics.components


Mon, 05 Sep 2005 01:58:19 GMT  
 FPGA specs

Quote:
> hi all
> What is the difference between he Typical gates and Maximum System gates
> specifications
> For Altera EPXA1 these ratings are 100K and 263K respectively  what may be
> the available gates for programming
> regards
> geeko

The other groups that you've cross-posted to should certainly have the info
you need. As would Altera if you ask them!


Mon, 05 Sep 2005 05:22:25 GMT  
 FPGA specs
The difference is Engineering and Marketting


Quote:


> > hi all
> > What is the difference between he Typical gates and Maximum System gates
> > specifications
> > For Altera EPXA1 these ratings are 100K and 263K respectively  what may
be
> > the available gates for programming
> > regards
> > geeko

> The other groups that you've cross-posted to should certainly have the
info
> you need. As would Altera if you ask them!



Fri, 09 Sep 2005 02:30:16 GMT  
 FPGA specs

Quote:

> hi all
> What is the difference between he Typical gates and Maximum System gates
> specifications
> For Altera EPXA1 these ratings are 100K and 263K respectively  what may be
> the available gates for programming
> regards
> geeko

I have not looked at the actual terms you are asking about, but my best
guess is that one tells you the capacity of the FPGA and the other is a
best estimate of how many of those gates are used by a typical design
that fits in the part.  Of course the number of gates in the design
depends entirely on the details of how the design fits the chip.  If
your design optimally uses the features of the chip you can see a much
higher gate count in the same chip as another design which just doesn't
make good use of the chip features.  

So in the real world, gates are not a good way to measure a chip.  You
will do much better to fit your design to the chip and see how well it
fits.  Or at least do a preliminary job of estimating by trying to
"guesstimate" the details of how your design will fit in the chip.  

--

Rick "rickman" Collins


Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



Sun, 11 Sep 2005 13:24:44 GMT  
 FPGA specs


Quote:

> > What is the difference between he Typical gates and Maximum System gates
> > specifications

(snip)

Quote:
> I have not looked at the actual terms you are asking about, but my best
> guess is that one tells you the capacity of the FPGA and the other is a
> best estimate of how many of those gates are used by a typical design
> that fits in the part.  Of course the number of gates in the design
> depends entirely on the details of how the design fits the chip.  If
> your design optimally uses the features of the chip you can see a much
> higher gate count in the same chip as another design which just doesn't
> make good use of the chip features.

> So in the real world, gates are not a good way to measure a chip.  You
> will do much better to fit your design to the chip and see how well it
> fits.  Or at least do a preliminary job of estimating by trying to
> "guesstimate" the details of how your design will fit in the chip.

I don't think the problem is so much different than processor speed
benchmarks.  Some people will calculate the maximum possible rate of
instruction execution and claim that as a speed, when no real problem would
ever do that.

-- glen



Sun, 11 Sep 2005 13:37:02 GMT  
 FPGA specs

Quote:
> > So in the real world, gates are not a good way to measure a chip.  You
> > will do much better to fit your design to the chip and see how well it
> > fits.  Or at least do a preliminary job of estimating by trying to
> > "guesstimate" the details of how your design will fit in the chip.

> I don't think the problem is so much different than processor speed
> benchmarks.  Some people will calculate the maximum possible rate of
> instruction execution and claim that as a speed, when no real problem would
> ever do that.

It should also be noted that these numbers usually include an
unexpected factor of two:
A 2-input AND gate counts as two equivalant gates, a 3-input and
counts as three, and so on.
(Apperently someone decided that it would be to complicated to call a
3-input gate 1.5 eqivalent gates.)

This nomenclature does not come from marketing but from academia and
is related to the literal count metric for circuit size.

A Flip-Flop typically counts as 6 gates.
And some vendors count a 4kBit Block-RAM as 4096 Flip-FLops.

Kolja Sulimma



Sun, 11 Sep 2005 20:45:56 GMT  
 FPGA specs
That is weird, and I am sure Marketing ( for all its other foibles) is
not responsible for this stupidity.  I also do not believe that this
silly method is part of FPGA gate counting.
When I was involved, we reduced everything to 2-input gates, and a 2-XOR
became 4 gates.

Peter Alfke
=========================

Quote:

> A 2-input AND gate counts as two equivalant gates, a 3-input and
> counts as three, and so on.
> (Apperently someone decided that it would be to complicated to call a
> 3-input gate 1.5 eqivalent gates.)

> This nomenclature does not come from marketing but from academia and
> is related to the literal count metric for circuit size.



Mon, 12 Sep 2005 01:51:29 GMT  
 FPGA specs

Quote:

> That is weird, and I am sure Marketing ( for all its other foibles) is
> not responsible for this stupidity.  I also do not believe that this
> silly method is part of FPGA gate counting.
> When I was involved, we reduced everything to 2-input gates, and a 2-XOR
> became 4 gates.

The more or less best utilization you can get out of a FPGA LE is a full
adder and a flip flop with asynchronous set or reset (or two of them for
Xilinx LC). I looked into one cell library, and these two count as 16 NAND2
gates (size, not transistor count); I used a scannable flip-flop, since
this is often required for testing, to blow up the number of gate
equivalents.

Unfortunately, this best case is not the usual case. Many flip-flops in
FPGAs are unused, and the logic table also is often used in a much simpler
way. A multiplexer (2.3 gate equivalents) already consumes a complete LE.
FPGA producers also count the SRAM cells as "gates". I don't know how many
gate equivalents they use, but my SRAM cell is the size of 0.5 NAND2 gates.

--
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/



Mon, 12 Sep 2005 18:15:49 GMT  
 FPGA specs


Quote:
> > > So in the real world, gates are not a good way to measure a chip.  You
> > > will do much better to fit your design to the chip and see how well it
> > > fits.  Or at least do a preliminary job of estimating by trying to
> > > "guesstimate" the details of how your design will fit in the chip.

(snip)

Quote:
> It should also be noted that these numbers usually include an
> unexpected factor of two:
> A 2-input AND gate counts as two equivalant gates,
> a 3-input and counts as three, and so on.
> (Apperently someone decided that it would be to complicated
>  to call a 3-input gate 1.5 eqivalent gates.)

> This nomenclature does not come from marketing but from academia and
> is related to the literal count metric for circuit size.

> A Flip-Flop typically counts as 6 gates.
> And some vendors count a 4kBit Block-RAM as 4096 Flip-FLops.

As far as I know, the convention since CMOS is to count the transistors and
divide by the number in a two input NAND gate, which is 4 for CMOS.  For
reasonably N, an N input CMOS NAND gate takes 2N transistors.

In TTL, an AND gate is pretty much a NAND followed by an inverter, and
probably does count as two.   But in TTL, an N input NAND takes the same
number of transistors and a 2 input NAND.

If one wanted a count of logic complexity, (how hard it is to design), as
opposed to how hard it is to fit on a chip, the numbers might be different.
Also, they work out completely differently for FPGA's.

-- glen



Tue, 13 Sep 2005 06:05:19 GMT  
 FPGA specs
Inspired by Goedel I conclude that there are more gate count metrics
then there are design to measure....

According to this application note:
http://www.xilinx.com/xapp/xapp059.pdf
Peter is right (at least for Xilinx measurements)

Here are the numbers:
Function Gate_Count
NAND2    1
MUX2     4
XOR3     6
XOR4     9
FA       9
DFF      6
DFF+Reset 8
DFF+R+CE 12

Kolja Sulimma

Quote:

> When I was involved, we reduced everything to 2-input gates, and a 2-XOR
> became 4 gates.

> > A 2-input AND gate counts as two equivalant gates, a 3-input and
> > counts as three, and so on.



Tue, 13 Sep 2005 07:25:31 GMT  
 
 [ 11 post ] 

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