Aggregate Selection With Variables (LRM Question) 
Author Message
 Aggregate Selection With Variables (LRM Question)

hi folks.  recently i tried acessing the bits in a vector by doing

for index in (23 downto 11) loop
    IRQ <= (index => '0', others => '1');
    -- etc....
end loop;

and got the following error from ModelSim :
Aggregate with multiple choices has a non-static choice.

of course, this was easily fixed by doing

for index in (23 downto 11) loop
    IRQ <= (others => '1'); IRQ(index) <= '0';
    -- etc...
end loop;

i don't have a problem with doing things this way.  i'm just wondering,
what's the rationale behind not allowing aggregate assignments
with variables?  is it a tool quirk or LRM mandate?  while the sinlge
assignment to the signal seems more intuitive, does it create more
overhead for the compiler?  or is it just not allowed?

Thanks.

RoLm

Sent via Deja.com http://www.*-*-*.com/
Share what you know. Learn what you don't.



Tue, 13 Nov 2001 03:00:00 GMT  
 Aggregate Selection With Variables (LRM Question)

Quote:
> hi folks.  recently i tried acessing the bits in a vector by doing
> for index in (23 downto 11) loop
>     IRQ <= (index => '0', others => '1');
>     -- etc....
> end loop;
> and got the following error from ModelSim :
> Aggregate with multiple choices has a non-static choice.
> of course, this was easily fixed by doing
> for index in (23 downto 11) loop
>     IRQ <= (others => '1'); IRQ(index) <= '0';
>     -- etc...
> end loop;
> i don't have a problem with doing things this way.  i'm just wondering,
> what's the rationale behind not allowing aggregate assignments
> with variables?  is it a tool quirk or LRM mandate?  while the sinlge
> assignment to the signal seems more intuitive, does it create more
> overhead for the compiler?  or is it just not allowed?

You misunderstand.  It has nothing to do with assignment, either to
variables or to signals.  It has to do with the construction of the
aggregate itself, no matter the purpose to which it is put.

(The) VHDL (LRM) requires that the choices be unique (no overlap) and
collectively cover the entire index range of the array subtype of this
value (in the case of an array aggregate).  If you don't have all
static choices in an aggregate, you force runtime checks.  The
designers of VHDL decided that forcing runtime checks was not a good
language design choice here.  Hence the requirement for static choices.

Hope this helps,

Paul

--

OrCAD                  | www.orcad.com   | spread fear, uncertainty and doubt
P.O. Box 71767         | 919-479-1670[v] | in the users' minds."
Durham, NC  27722-1767 | 919-479-1671[f] |    --Don Jones, MS's Y2K Product Mgr



Tue, 13 Nov 2001 03:00:00 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. variable assignment with target as aggregate

2. Need help on aggregates in variable assignments !!!

3. diff Ada83-LRM Ada9X-LRM

4. Draft B of VHDL LRM - Shared Variables

5. Wierd question with aggregates and initialization

6. Question: Aggregate target

7. aggregate questions

8. Aggregate Target assignment question

9. aggregate syntax question

10. Record aggregate question (language lawyer needed!)

11. Questions about LRM

12. Verilog LRM 2.0 question

 

 
Powered by phpBB® Forum Software