Q: universal expressions 
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 Q: universal expressions

Section 7.5 of the LRM Std 1076-87 declares the following mixed-type
operations:
        universal_real * universal_integer => universal_real
        universal_integer * universal_real => universal_real
        universal_real / universal_integer => universal_real

From that I would expect that a VHDL analyser should understand
        real_var := 100.0 / 10;
but not
        real_var := 100 / 10.0;

What is the reason for the missing symmetry operation
        universal_integer / universal_real => universal_real
?

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Fri, 25 Oct 1996 23:42:47 GMT  
 
 [ 1 post ] 

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