selected signal assignment question 
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 selected signal assignment question

How can I make this work with FPGA Express ?

this:
with Address(7 downto 0) select
  ReadData <=
  GenePeriod(7 downto 0)                                      when
"00000000",
  DDSData                                                     when
"1XXXXXXX",
  "01010101"                                                  when others;
is accepted but does not work

this:
  DDSData   when "10000000" to "11111111",
is not accepted

this:
  DDSData  when "10000000" | "10000001" | "10000010",
works but I would avoid to put 64 constants...

Any ideas ?

Thanks

Marc Battyani



Sat, 19 Oct 2002 03:00:00 GMT  
 selected signal assignment question

Quote:

> How can I make this work with FPGA Express ?

> this:
> with Address(7 downto 0) select
>   ReadData <=
>   GenePeriod(7 downto 0)                                      when
> "00000000",
>   DDSData                                                     when
> "1XXXXXXX",
>   "01010101"                                                  when others;
> is accepted but does not work

Have you tried "1-------"? This might work. Otherwise, you might
consider using an IF Address(7) = '1' THEN ReadData <= DDSData; ELSE...

Be careful, '-' might work differently in some simulators and
synthesis engines.

chm.

--

utanet.at  -  Vienna/Austria/Europe



Sat, 19 Oct 2002 03:00:00 GMT  
 selected signal assignment question
Hi,

Quote:


> > How can I make this work with FPGA Express ?

> > this:
> > with Address(7 downto 0) select
> >   ReadData <=
> >   GenePeriod(7 downto 0)                                      when
> > "00000000",
> >   DDSData                                                     when
> > "1XXXXXXX",
> >   "01010101"                                                  when others;
> > is accepted but does not work

> Have you tried "1-------"? This might work. Otherwise, you might
> consider using an IF Address(7) = '1' THEN ReadData <= DDSData; ELSE...

> Be careful, '-' might work differently in some simulators and
> synthesis engines.

I just want to amplify the warning: a choice "1-------"
will NOT work as intended with the simulator (although
the synthesis tool might accept it as intended)!!!

Actually, the states '-', 'X', 'U', ... are just states (characters)
like '0' and '1'  for the VHDL compiler.  VHDL does not evaluate
"don't cares". See section 4.2.9 (part 1) of the FAQ
(http://www.vhdl.org/comp.lang.vhdl/)  for some further info.

Another solution to your problem might be to convert the address
vector to integer:

with to_integer(unsigned(Address(7 downto 0))) select
    ReadData <=
        ... when 0,
        ... when 128 to 255;

I assume that Address is an std_logic_vector.

--
Edwin



Sun, 20 Oct 2002 03:00:00 GMT  
 selected signal assignment question

Quote:

> with Address(7 downto 0) select
>   ReadData <=
>   GenePeriod(7 downto 0)                                      when
> "00000000",
>   DDSData                                                     when
> "1XXXXXXX",
>   "01010101"                                                  when others;

Try the following:

library ieee;
use ieee.numeric_std.all;

ReadData <=  GenePeriod(7 downto 0)  when Std_Match(Address(7 downto 0),
"00000000")  else
                           DDSData                              when
Std_Match(Address(7 downto 0), "1-------") else
                            "01010101";

--
Kerry Imming
Network Processor  Development, IMD Rochester



Sun, 20 Oct 2002 03:00:00 GMT  
 selected signal assignment question
Thanks to all,

This seems to work well for synthesis with FPGA Express

with conv_integer(Address(7 downto 0)) select
  ReadData <=
  GenePeriod(7 downto 0)                    when 0,
  "0000" & GenePeriod(11 downto 8)  when 1,
  "10101010"                                       when 30,
  DDSData                                           when 128 to 255,

etc...

Marc Battyani



Mon, 21 Oct 2002 03:00:00 GMT  
 
 [ 5 post ] 

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