inertial vs. transport delay 
Author Message
 inertial vs. transport delay

A question for those of you out there who have done "real" designs in
VHDL.  Did you establish any general rules or guidelines for using
inertial vs. transport delay in your models?  If you did, would you be
willing to share those guidelines with me?

Suppose you were given a VHDL description of a device at the data-flow
level using primitives such as and, or, etc., and it was claimed that
the actual design would closly match the data-flow description.
(Assume you were going to automatically translate the primitive
operations to gates in the obvious way.)  Would you feel more
confident that the resulting hardware would work if the VHDL model
used inertial delay, or if it used transport delay?  Why?

I will post an analysis of my responses if there is enough interest.

Larry M. Augustin                       ERL 414


(415) 723-9285                          Stanford, CA 94305



Tue, 29 Mar 1994 00:58:11 GMT  
 
 [ 1 post ] 

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