test benching using file input 
Author Message
 test benching using file input

Hello fellow VHDL implementors.

I was wondering if any of you have had and tremendous success with test-
benching.  My goal is to eventually be able to have a VHDL model of
an n-channel tester, and to be able to read a configuration file,
and then a vector file to apply stimulus and test assertions.  Don't
worry about this problem for now.  I have some simpler questions to
begin with.

Suppose I have a stimulus file.  I would like each line to contain
a timestamp followed by signal groups.  For example, two lines in the
vector file might look like this:

25ns: 1 AF30 1010 1
50ns: 0 ZZZZ 0101 1

Now, the first field is a clock, which always has a binary value
of 1 or 0.  The second field is an address bus.  This is a hard
part for me.  How do I read in that hexadecimal value and convert
it to a std_logic_vector?  Does anyone have any example code for
that?  My second problem with this address bus is, how do I release
it if "ZZZZ" is present?  I want to "release the force" in simulator
terminology, rather than to force the bus to "ZZZZ".

The third field is a bus, but it is "flattened" to be binary.  Is
there a one-step way using textio to read this into a bit-vector,
or do I need to do a character to bit-vector conversion?  Does anyone
have example code for this?

Thanks for any help.  Please e-mail me (with the option to post for
other readers) since our news reader sometimes loses messages.  If
you didn't notice, I am pretty much new to VHDL, but will become a
powerful adversary to VHDL opponents if I get some help with these
tasks.  I can model parts and stuff, but I don't have any good examples
of using the textio package and doing string parsing or conversions.


Martin Marietta Corporation                     phone:       (609) 866-6546  
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Thu, 06 Mar 1997 02:46:03 GMT  
 [ 1 post ] 

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