test benching using file input 
Author Message
 test benching using file input

Hello fellow VHDL implementors.

I was wondering if any of you have had and tremendous success with test-
benching.  My goal is to eventually be able to have a VHDL model of
an n-channel tester, and to be able to read a configuration file,
and then a vector file to apply stimulus and test assertions.  Don't
worry about this problem for now.  I have some simpler questions to
begin with.

Suppose I have a stimulus file.  I would like each line to contain
a timestamp followed by signal groups.  For example, two lines in the
vector file might look like this:

25ns: 1 AF30 1010 1
50ns: 0 ZZZZ 0101 1

Now, the first field is a clock, which always has a binary value
of 1 or 0.  The second field is an address bus.  This is a hard
part for me.  How do I read in that hexadecimal value and convert
it to a std_logic_vector?  Does anyone have any example code for
that?  My second problem with this address bus is, how do I release
it if "ZZZZ" is present?  I want to "release the force" in simulator
terminology, rather than to force the bus to "ZZZZ".

The third field is a bus, but it is "flattened" to be binary.  Is
there a one-step way using textio to read this into a bit-vector,
or do I need to do a character to bit-vector conversion?  Does anyone
have example code for this?

Thanks for any help.  Please e-mail me (with the option to post for
other readers) since our news reader sometimes loses messages.  If
you didn't notice, I am pretty much new to VHDL, but will become a
powerful adversary to VHDL opponents if I get some help with these
tasks.  I can model parts and stuff, but I don't have any good examples
of using the textio package and doing string parsing or conversions.

        -Jon
____________________________________________________________________________

Martin Marietta Corporation                     phone:       (609) 866-6546  
Advanced Technology Laboratories                dial comm:       8*777-6546
Building 145-2                                  FAX:         (609) 866-6397
Moorestown, NJ 08057
____________________________________________________________________________



Thu, 06 Mar 1997 02:46:03 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. problem with Test Bench using ModelSim

2. test bench hierarchical design using processes

3. Synopsys test bench to Mentor Force file translator

4. Help on opening multiple input files(test vector files)

5. Accessing VHDL signals from Verilog test bench

6. Bus models, Test benches

7. Is there any script for integrated such as test-bench, top-level

8. DS1 and DS3 test benches

9. test bench for usb interface

10. test bench

11. Interfacing an ISS C model to a Verilog test bench

12. AD: Cheap Test Bench tool

 

 
Powered by phpBB® Forum Software