Scope of signals seen from subprogram 
Author Message
 Scope of signals seen from subprogram

Hi,

I'm trying to compile the following under Modelsim 5.4b (command line
vsim -93 whatever.vhd):

entity test is
end test;

architecture test of test is

signal test : integer;

procedure test_proc is
begin
  test <= 0;
end test_proc;

begin
end test;

and it gives the error "Cannot drive signal test from this subprogram."
on the line "test <= 0;".

It compiles without problem under Simili (Hi Haneef!).  I've browsed the
LRM and Ashenden, and can't see anything that would indicate that this
code shouldn't compile.

Is this a modelsim bug?  Or aren't we allowed to write to signals from
procedures declared before the "begin"?

Ta,
Allan.
--

Agilent Technologies          Voice:  +61 3 9210 5527
Advanced Networks Division    Fax:    +61 3 9210 5550
347 Burwood Highway  Forest Hill 3131 Australia



Sun, 26 Jan 2003 03:00:00 GMT  
 Scope of signals seen from subprogram
Hi,

You must give the signal to the procedure as a parameter.

Like this:

procedure test_proc (signal test : out integer) is
begin
  test <= 0;
end test_proc;

BR,
    Jyke

Quote:

>Hi,

>I'm trying to compile the following under Modelsim 5.4b (command line
>vsim -93 whatever.vhd):

>entity test is
>end test;

>architecture test of test is

>signal test : integer;

>procedure test_proc is
>begin
>  test <= 0;
>end test_proc;

>begin
>end test;

>and it gives the error "Cannot drive signal test from this subprogram."
>on the line "test <= 0;".

>It compiles without problem under Simili (Hi Haneef!).  I've browsed the
>LRM and Ashenden, and can't see anything that would indicate that this
>code shouldn't compile.

>Is this a modelsim bug?  Or aren't we allowed to write to signals from
>procedures declared before the "begin"?

>Ta,
>Allan.
>--

>Agilent Technologies          Voice:  +61 3 9210 5527
>Advanced Networks Division    Fax:    +61 3 9210 5550
>347 Burwood Highway  Forest Hill 3131 Australia



Sun, 26 Jan 2003 03:00:00 GMT  
 Scope of signals seen from subprogram
Hi,
   You are correct about the visibility of the signal "test" which is
declared in the architecture declaration part within the PROCEDURE
"test-proc" - BUT there is a gotcha! i.e. since this procedure has no formal
parameters and is trying to modify or "drive" a signal which is NOT in the
formal parameter list, such a transaction is ILLEGAL. This is b'cos there is
*no real owner* for the signal driver (if in case this procedure is declared
within a process, then that process will be the *owner* for this signal
driver) and that's is why it is illegal.

A possible remedy could be to add the signal in the formal parameter list
(which is safer and decent way to do, else you get to see *side effects*).
So ModelSim is quite right and not the Simli (Dear haneef, would you please
take this into a/c in your future release?).

Hope this helps,
Srini

For more (with a good example) visit:

http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#procedure_drivers

Here is an extract from the above link:

4.2.13 Procedures and Drivers
Procedures may contain signal assignment statements. In this case, the
driver or drivers (see FAQ Part 4 - B.78) corresponding to these assignments
are not associated with the procedure, but with the process(es) calling the
procedure. As stated in Section 4.2.12, VHDL needs to be able to statically
determine all drivers of a signal. Hence, unless the procedure is declared
within a process (and therefore callable only by the process), the procedure
must drive only signals passed as parameters to the procedure. This
restriction allows the elaborator to determine the signals that are driven
by a given process, so that the drivers for the process can be identified
during elaboration.


Quote:
> Hi,



Sun, 26 Jan 2003 03:00:00 GMT  
 Scope of signals seen from subprogram

Quote:

> and it gives the error "Cannot drive signal test from this subprogram."
> on the line "test <= 0;".

> It compiles without problem under Simili (Hi Haneef!).  I've browsed the
> LRM and Ashenden, and can't see anything that would indicate that this
> code shouldn't compile.

> Is this a modelsim bug?  Or aren't we allowed to write to signals from
> procedures declared before the "begin"?

Hi Allan,

ModelSim is correct. Simili should have also produced
an error at compile time. If you actually try to
simulate this simili will also give you an error. I
will see how I can produce this error at compile time.
Thanx for the heads up...

This is the error message you will see in Simili during
elaboration....

    Error: CSVHE0023: x.vhd: (line 10): Bad signal assignment. Target is not a subprogram parameter and the containing
subprogram does not have an enclosing process

As others have explained, it is indeed illegal. If you had declared
the procedure in a process, then it would have been legal....this
essentially forces the procedure definition and the call into the same
process and the driver for the signal can be associated with a
particular process. Also, if the procedure was called multiple times
from the same process, it would still create a single driver.

The best thing might be to pass this signal as a parameter which
makes the procedure more versatile....

Regards,
Haneef



Sun, 26 Jan 2003 03:00:00 GMT  
 
 [ 4 post ] 

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