Meta stable singals in vital model 
Author Message
 Meta stable singals in vital model

Quote:

> I'm trying to find a way of modeling a meta stable signal in a vital
> simulation.
> If I double buffer the write signal using:
> process (clk)
> if clk'event and clk = '1' then
>   write_stable <= write_meta;
>   write_meta <= write_input;
> end if;
> end process;
> Then quite correctly the write_stable signal will become X for one
> clock cycle.
> The problem is that I then want to produce a one clock long enable
> signal on a rising edge of the write using.
> process(clk)
> if clk'event and clk= '1' then
>   write_delayed <= write_stable;
> end if;
> end process;
> enable <= write_stable AND NOT write_delayed;
> enable will go 0XX0 and so will never count as being active even
> though we know it will be high for one of the two X's, just not
> which one.
> Is there any way of getting around this problem other than making
> sure the meta-stable condition never occurs?

How about:

        process(clk)
        begin
          if rising_edge(clk)  -- more reliable than "clk='1' and clk'event"
          then
            write_meta   <= write_input;
            write_stable <= write_meta;

            if rising_edge(write_input) then
              enable <= '1';
            else
              enable <= '0';
            end if;
          end if;
        end process;

Paul

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Fri, 24 Aug 2001 03:00:00 GMT  
 Meta stable singals in vital model

Quote:

>enable <= write_stable AND NOT write_delayed;

>enable will go 0XX0 and so will never count as being active even though we
>know it will be high for one of the two X's, just not which one.

i'm not sure that i understand this - isn't 0000 possible in the real
implementation?

1)  write_stable and write_delayed start at zero
2)  on the first clock, w_s goes to x
3)  on the second clock, the simulated output is (x and not 0),
    which is x.
    on the real hardware, the x on w_s may be interpreted as a 0,
    in which case the real output is 0.
4)  on the third clock, the simulated output is (1 and not x),
    which is x.
    on the real hardware, the x on w_d may be interpreted as 1,
    in which case the real output is 0.
5)  on the 4th clock, both the real and simulated outputs are 0.

in other words, the simulation correctly gives 0xx0, and the real
hardware has never produced a high-going pulse.

Quote:
>Is there any way of getting around this problem other than making sure the
>meta-stable condition never occurs?

i think there are several, but i suspect that you wont be able to use
paul's (if you're simulating a synthesised netlist, in which case
you'll have a limited ability to change the code). some possible
options:

1) your VITAL F/F model will probably have two generics called
'TimingChecksOn' and 'Xon'. you can turn one or both of these off, for
the first F/F in the synchro chain. if you turn off TimingChecksOn,
you won't get an x, and if you turn off Xon, the x will be generated
as a 0 or a 1 (i forget which).

to turn them off, write a configuration for the simulation, with an
explicit entry for the synchro f/f, and set these values in the
generic map.

2) in real life, you're expecting the x on the first synchro to settle
to a 0 or a 1 by the end of the clock cycle. the VITAL model simply
leaves it as an x throughout the cycle, and you could try to 'fix'
this, by forcing it to a 0 or 1, when you think it's going to be
stable (hopefully before the next clock edge - if not, you haven't got
enough F/Fs in your chain...)

this is much harder than (1) above.

evan



Fri, 24 Aug 2001 03:00:00 GMT  
 
 [ 4 post ] 

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