Internal Nodes of an XOR tree
Author Message
Internal Nodes of an XOR tree

Hi,
I have generated an XOR tree using a recursive entity, with a generic
(512). However, I'd like to access every node in the tree, brought out
as a signal in a generic way (depending on the size of the tree). Has
anyone got an idea of how to do it in VHDL?
Yves
Here is a piece of the code:

entity xor_tree is
generic (height: positive:= 512);
port (input: in std_ulogic_vector(2**height-1 downto 0);
output: out std_ulogic);
end entity xor_tree;

architecture recursive of xor_tree is
signal bottom_output, top_output: std_ulogic;
begin
BASE: if height = 1 generate
begin
output <= input(1) xor input(0);
end generate;

SUBTREE: if height > 1 generate
begin
BOTTOM_TREE: component xor_tree
generic map (height => (height - 1))
port map (input => input(2**height-1 downto 2**(height-1)),
output => bottom_output);

TOP_TREE: component xor_tree
generic map (height => (height - 1))
port map (input => input(2**(height-1)-1 downto 0),
output => top_output);

output <= bottom_output xor top_output;
end generate;

end architecture recursive;

Sat, 11 Dec 2004 00:27:33 GMT
Internal Nodes of an XOR tree
Represent the tree as a one dimensional vector.  You can write a function
that calculates the tree area and sets that as the vector size:

architecture behave of big_xor is
function FN_CALC_NODES( height : integer ) return integer is
...
end

constant NODE_CNT : integer := FN_CALC_NODES ;
subtype NODE_VEC is std_logic_vector( NODE_CNT - 1 downto 0 ) ;
signal nodes : NODE_VEC ;
...

Then you will need to keep a running count of the node index and map your
internal signals to the appropriate element.  In that regard, a function
that returns a structure may be useful.

Regards

Quote:
> Hi,
> I have generated an XOR tree using a recursive entity, with a generic
> (512). However, I'd like to access every node in the tree, brought out
> as a signal in a generic way (depending on the size of the tree). Has
> anyone got an idea of how to do it in VHDL?
> Yves
> Here is a piece of the code:

> entity xor_tree is
>  generic (height: positive:= 512);
>  port (input: in std_ulogic_vector(2**height-1 downto 0);
>        output: out std_ulogic);
> end entity xor_tree;

> architecture recursive of xor_tree is
>  signal bottom_output, top_output: std_ulogic;
> begin
>  BASE: if height = 1 generate
>  begin
>   output <= input(1) xor input(0);
>  end generate;

>  SUBTREE: if height > 1 generate
>  begin
>   BOTTOM_TREE: component xor_tree
>   generic map (height => (height - 1))
>   port map (input => input(2**height-1 downto 2**(height-1)),
>             output => bottom_output);

>   TOP_TREE: component xor_tree
>   generic map (height => (height - 1))
>   port map (input => input(2**(height-1)-1 downto 0),
>             output => top_output);

>   output <= bottom_output xor top_output;
>  end generate;

> end architecture recursive;

Sat, 11 Dec 2004 16:01:55 GMT

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