Clock skew problem 
Author Message
 Clock skew problem

Hello,

I having a problem with a signal which needs to be connected to d-flipflop
clock input which is not a globally defined clock such as used with flex10k
devices.

The problem is very fundemental one:
A change in a signal must occur after a clock change from low->high and not
before it.

I'm having this problem with a shift register:
suppose we have:

DFF1.clk= semiclk
DFF2.clk= semiclk + delay1

DFF1.q= DFF2.d (after delay2)

I need to be sure that delay2 > delay1 + holdtime(DFF2)?
How do I accomplish this? Can I assign a special status to my clk line which
cant be a globally defined clock line?

Regards,

Jasper



Fri, 31 Jan 2003 03:00:00 GMT  
 Clock skew problem
Hello Jasper!

I have had this problem with shift registers (and counters) and clock skew
too, and I found no other solution than to put an
extra DFF between the "problem" DFFs, and clock that extra flipflop on the
opposite clock edge. It cost's some hardware,
but I don't have to worry about clock skew any more, as long as the clock
frequency allows this solution.

Best regards

Thomas



Quote:
> Hello,

> I having a problem with a signal which needs to be connected to d-flipflop
> clock input which is not a globally defined clock such as used with
flex10k
> devices.

> The problem is very fundemental one:
> A change in a signal must occur after a clock change from low->high and
not
> before it.

> I'm having this problem with a shift register:
> suppose we have:

> DFF1.clk= semiclk
> DFF2.clk= semiclk + delay1

> DFF1.q= DFF2.d (after delay2)

> I need to be sure that delay2 > delay1 + holdtime(DFF2)?
> How do I accomplish this? Can I assign a special status to my clk line
which
> cant be a globally defined clock line?

> Regards,

> Jasper



Sun, 02 Feb 2003 03:00:00 GMT  
 
 [ 2 post ] 

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