clocking on rising AND falling edge of a clock 
Author Message
 clocking on rising AND falling edge of a clock

Hi all,

Can anybody tell me how I can clock a process on the rising AND falling edge
of  a clock signal ?

I want to do something like :
<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
but it doesn't work.

Please help
Abraham



Mon, 08 Mar 2004 16:50:48 GMT  
 clocking on rising AND falling edge of a clock

Quote:
> Hi all,

> Can anybody tell me how I can clock a process on the rising AND
> falling edge of a clock signal ?

> I want to do something like : <<<<<if (clock_in'event and clock_in='1'
> and clock_in='0') then >>>>> but it doesn't work.

> Please help Abraham

Perhaps
if (clock'event) then
 <statements>
end if;

or maybe clearer?
if (rising_Edge(clock) or falling_edge(clock)) then ...

Of course, it won't be very synthesisable - unless you have access to
FF which can be clocked on both edges.

HTH,
Martin

--

TRW Automotive Technical Centre, Solihull, UK



Mon, 08 Mar 2004 17:04:57 GMT  
 clocking on rising AND falling edge of a clock
nope. the rising_edge feature doesn't work

Quote:

> > Hi all,

> > Can anybody tell me how I can clock a process on the rising AND
> > falling edge of a clock signal ?

> > I want to do something like : <<<<<if (clock_in'event and clock_in='1'
> > and clock_in='0') then >>>>> but it doesn't work.

> > Please help Abraham

> Perhaps
> if (clock'event) then
>  <statements>
> end if;

> or maybe clearer?
> if (rising_Edge(clock) or falling_edge(clock)) then ...

> Of course, it won't be very synthesisable - unless you have access to
> FF which can be clocked on both edges.

> HTH,
> Martin

> --

> TRW Automotive Technical Centre, Solihull, UK



Mon, 08 Mar 2004 17:48:17 GMT  
 clocking on rising AND falling edge of a clock

Quote:

>>>Can anybody tell me how I can clock a process on the rising AND
>>>falling edge of a clock signal ?

if ( clk'event AND ((clk = '1' AND clk'last_value = '0') OR (clk = '0' AND clk'last_value = '1')) then

...

This code checks for a clock event and a valid rising or falling edge

Ludwig

--


Senior Software Engineer        Frontier Design, Belgium
__________________________________________________________________



Mon, 08 Mar 2004 18:14:01 GMT  
 clocking on rising AND falling edge of a clock


Quote:
> nope. the rising_edge feature doesn't work

What do you mean by "doesn't work"? It will work for std_logic &
std_ulogic signals. If your clock is bit, you will need
ieee.numeric_bit package.

BTW, from a pure modelling perspective

process (clk)
begin
 a <= not a;
end

should trigger on both the edges of clock.

Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)



Mon, 08 Mar 2004 19:26:22 GMT  
 clocking on rising AND falling edge of a clock



Quote:
> Hi all,

> Can anybody tell me how I can clock a process on the rising AND falling edge
> of  a clock signal ?

> I want to do something like :
> <<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
> but it doesn't work.

> Please help
> Abraham

I think you mean OR, not AND

    if (clock_in'event and (clock_in='1' OR clock_in='0'))

This is OK for sim.  For synth, check the archives...



Mon, 08 Mar 2004 19:58:14 GMT  
 clocking on rising AND falling edge of a clock
This type of problem is not well supported for synthesis. Much better would
be if you have a high speed clock you can use to sample the your clock for
both edges.

Another method would be to use a PLL to double the clock frequency, such as
are available in larger FPGAs.

Ian.



Quote:
> Hi all,

> Can anybody tell me how I can clock a process on the rising AND falling
edge
> of  a clock signal ?

> I want to do something like :
> <<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
> but it doesn't work.

> Please help
> Abraham



Fri, 12 Mar 2004 16:54:30 GMT  
 clocking on rising AND falling edge of a clock

Quote:

> This type of problem is not well supported for synthesis. Much better would
> be if you have a high speed clock you can use to sample the your clock for
> both edges.

> Another method would be to use a PLL to double the clock frequency, such as
> are available in larger FPGAs.

Xilinx Virtex and spartanII families have Delay lock loops even in the smallest
(15K gates) devices.  The DLLs can be used to double clocks.

Quote:

> Ian.



> > Hi all,

> > Can anybody tell me how I can clock a process on the rising AND falling
> edge
> > of  a clock signal ?

> > I want to do something like :
> > <<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
> > but it doesn't work.

> > Please help
> > Abraham

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Fri, 12 Mar 2004 20:48:42 GMT  
 
 [ 8 post ] 

 Relevant Pages 

1. rise and fall edge clock processes

2. USE both rising edge and falling edge

3. USE both rising edge and falling edge

4. Why Not Use Clock Falling Edge?

5. clock scan [clock format [clock seconds]] fails

6. rising and falling edge

7. both rising/falling edges trigger state machine

8. Rising and falling edge

9. Working with falling and rising edge level

10. Detecting a signal rising/falling edge

11. rising/falling edge detector

12. Clocking both edges

 

 
Powered by phpBB® Forum Software